aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | | gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
|/ /
* | Merge pull request #1507 from YosysHQ/clifford/verificfixesClifford Wolf2019-11-202-6/+9
|\ \
| * | Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| * | Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
|/ /
* | Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1927-89/+841
|\ \
| * | Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| * | add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
| |\ \
| * | | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
| |\ \ \
| * | | | fix wide lutsPepijn de Vos2019-11-062-19/+22
| * | | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| * | | | add IOBUFPepijn de Vos2019-10-282-1/+10
| * | | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
| * | | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| * | | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
| * | | | More formattingPepijn de Vos2019-10-281-55/+49
| * | | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| * | | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| * | | | add wide lutsPepijn de Vos2019-10-283-36/+119
| * | | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| * | | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
| * | | | Add some testsPepijn de Vos2019-10-2110-0/+224
| * | | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| * | | | add negedge DFFPepijn de Vos2019-10-212-15/+139
| * | | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
| * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
| |\ \ \ \
| * | | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
| * | | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| * | | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
| * | | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
| * | | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
| * | | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
| * | | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
| * | | | | add MUX supportPepijn de Vos2019-09-053-0/+17
| * | | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
| * | | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
| * | | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
| * | | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
| |\ \ \ \ \
| | * | | | | Updating gowinDiego H2019-09-022-2/+2
| * | | | | | Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| * | | | | | Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| * | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosysPepijn de Vos2019-09-043-5/+6
| |\ \ \ \ \ \
| * | | | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
* | | | | | | | Fix #1462, #1480.Marcin Kościelnicki2019-11-194-9/+40
* | | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| |_|_|_|_|_|/ |/| | | | | |
* | | | | | | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fixClifford Wolf2019-11-182-4/+21
|\ \ \ \ \ \ \
| * | | | | | | Fix #1496.Marcin Kościelnicki2019-11-182-4/+21
* | | | | | | | Merge pull request #1494 from whitequark/write_verilog-extmemwhitequark2019-11-181-10/+80
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | |
| * | | | | | | write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-18 00:16:09 +0000