| Commit message (Expand) | Author | Age | Files | Lines |
* | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 |
* | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 |
* | Merge pull request #841 from mmicko/master | Clifford Wolf | 2019-03-01 | 1 | -2/+3 |
|\ |
|
| * | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 |
|/ |
|
* | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
* | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode | Clifford Wolf | 2019-02-28 | 1 | -2/+2 |
|\ |
|
| * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 |
* | | Hotfix for "make test" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
* | | Merge pull request #837 from YosysHQ/clifford/fix835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 |
|\ \ |
|
| * | | Fix multiple issues in wreduce FF handling, fixes #835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 |
|/ / |
|
* | | Merge pull request #834 from YosysHQ/clifford/siminit | Clifford Wolf | 2019-02-28 | 2 | -3/+12 |
|\ \ |
|
| * | | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 2 | -3/+12 |
|/ / |
|
* | | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 9 | -29/+29 |
* | | Fix pmgen for in-tree builds | Clifford Wolf | 2019-02-28 | 2 | -8/+9 |
* | | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 7 | -12/+388 |
|\ \ |
|
| * | | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 2 | -0/+20 |
| * | | ecp5: Add DDRDLLA | David Shah | 2019-02-19 | 1 | -0/+9 |
| * | | ecp5: Add DELAYF/DELAYG blackboxes | David Shah | 2019-02-19 | 1 | -0/+18 |
| * | | ecp5: Add ECLKSYNCB blackbox | David Shah | 2019-02-13 | 1 | -1/+7 |
| * | | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 |
| * | | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 |
| * | | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 |
| * | | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 |
| * | | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 |
* | | | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 4 | -11/+21 |
|\ \ \
| |_|/
|/| | |
|
| * | | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 4 | -11/+21 |
* | | | Fix pmgen for out-of-tree build | Clifford Wolf | 2019-02-28 | 2 | -4/+6 |
* | | | Merge pull request #833 from YosysHQ/clifford/fix831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 |
|\ \ \ |
|
| * | | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 |
|/ / / |
|
* | | | Merge pull request #832 from YosysHQ/supercover | Clifford Wolf | 2019-02-28 | 2 | -0/+93 |
|\ \ \ |
|
| * | | | Improvements in "supercover" pass | Clifford Wolf | 2019-02-27 | 1 | -2/+18 |
| * | | | Add "supercover" skeleton | Clifford Wolf | 2019-02-27 | 2 | -0/+77 |
|/ / / |
|
* | | | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module | Larry Doolittle | 2019-02-26 | 1 | -22/+22 |
* | | | Clean up some whitepsace outliers | Larry Doolittle | 2019-02-26 | 3 | -6/+6 |
|/ / |
|
* | | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to... | Clifford Wolf | 2019-02-24 | 1 | -5/+1 |
* | | Merge pull request #812 from ucb-bar/arrayhierarchyfixes | Clifford Wolf | 2019-02-24 | 3 | -11/+108 |
|\ \ |
|
| * | | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 3 | -11/+14 |
| * | | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 3 | -10/+74 |
| * | | Define basic_cell_type() function and use it to derive the cell type for arra... | Jim Lawson | 2019-02-15 | 1 | -10/+40 |
* | | | Cleanups in ARST handling in wreduce | Clifford Wolf | 2019-02-24 | 1 | -10/+4 |
* | | | Merge pull request #824 from litghost/fix_reduce_on_ff | Clifford Wolf | 2019-02-24 | 3 | -0/+37 |
|\ \ \ |
|
| * | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | Keith Rothman | 2019-02-22 | 3 | -0/+37 |
* | | | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 2 | -0/+6 |
* | | | | Check if Verific was built with DB_PRESERVE_INITIAL_VALUE | Clifford Wolf | 2019-02-24 | 1 | -0/+4 |
* | | | | Merge pull request #819 from YosysHQ/clifford/optd | Clifford Wolf | 2019-02-22 | 1 | -2/+16 |
|\ \ \ \ |
|
| * | | | | Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine" | Clifford Wolf | 2019-02-21 | 1 | -3/+3 |
| * | | | | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior | Clifford Wolf | 2019-02-21 | 1 | -2/+16 |
* | | | | | Merge pull request #820 from YosysHQ/clifford/fix810 | Clifford Wolf | 2019-02-22 | 5 | -54/+26 |
|\ \ \ \ \ |
|
| * | | | | | Fix Travis | Clifford Wolf | 2019-02-22 | 3 | -42/+11 |
| * | | | | | Fixes related to handling of autowires and upto-ranges, fixes #814 | Clifford Wolf | 2019-02-21 | 2 | -9/+12 |