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* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-231-1/+1
* Improved handling of dff with async resetsClifford Wolf2013-10-212-5/+99
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-192-8/+21
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-182-2/+2
* Added dffsr support to proc_dff passClifford Wolf2013-10-181-7/+72
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-182-0/+13
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-181-8/+8
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-181-0/+181
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-183-0/+181
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-183-49/+80
* Improved way of connecting ports in techmap passClifford Wolf2013-10-171-18/+36
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-171-5/+6
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-171-2/+40
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-171-2/+7
* Avoid re-arranging signals on register outputsClifford Wolf2013-10-171-3/+31
* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-171-0/+3
* Added iopadmap passClifford Wolf2013-10-164-2/+167
* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-166-11/+10
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-161-2/+39
* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-161-1/+4
* Added recommended apt-get commands to READMEClifford Wolf2013-10-111-2/+20
* Fixed minisat includeClifford Wolf2013-10-111-1/+1
* Pinned ABC revision to 0f9e5488ced3Clifford Wolf2013-10-031-1/+3
* Improvements in EDIF backendClifford Wolf2013-09-172-2/+41
* Added additional options to BLIF backendClifford Wolf2013-09-151-15/+60
* Added BLIF backendClifford Wolf2013-09-152-0/+245
* A couple of small fixes in SPICE backendClifford Wolf2013-09-151-6/+18
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-1513-17/+17
* Updated manualClifford Wolf2013-09-153-21/+173
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-145-6/+73
* Added spice backendClifford Wolf2013-09-146-0/+306
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-032-10/+41
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-281-3/+16
| * Improved edif backendClifford Wolf2013-08-271-8/+18
| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-271-2/+10
* | Added -selected option to various backendsClifford Wolf2013-09-033-9/+58
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-224-0/+167
* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-221-13/+61
* Added edif backend (still under construction)Clifford Wolf2013-08-222-0/+202
* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-211-0/+2
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| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-211-0/+2
* | Some minor documentation fixesClifford Wolf2013-08-212-2/+2
* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-203-4/+24
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| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-203-4/+24
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-202-4/+8
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| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-202-4/+8
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* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-201-1/+2
* Added version info to yosys command and added -V optionClifford Wolf2013-08-203-2/+22
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-202-5/+5
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