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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-17 22:10:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-17 22:10:55 +0200 |
| commit | 8cc53ef72c5b65d33a3fb3c2467ce32c961bab91 (patch) | |
| tree | 715c327d2a6da64e18e3cb573ba424c4c8ed7e3e | |
| parent | 30b0de006f50f4c9234d86d3c1986846c27a72ae (diff) | |
| download | yosys-8cc53ef72c5b65d33a3fb3c2467ce32c961bab91.tar.gz yosys-8cc53ef72c5b65d33a3fb3c2467ce32c961bab91.tar.bz2 yosys-8cc53ef72c5b65d33a3fb3c2467ce32c961bab91.zip | |
Only prefer connected signals iff they have public names
| -rw-r--r-- | passes/opt/opt_clean.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index d76dafb3c..21ef320e2 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -112,11 +112,12 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool ® if (w1->port_input != w2->port_input) return w2->port_input; - if (regs.check_any(s1) != regs.check_any(s2)) - return regs.check_any(s2); - - if (conns.check_any(s1) != conns.check_any(s2)) - return conns.check_any(s2); + if (w1->name[0] == '\\' && w2->name[0] == '\\') { + if (regs.check_any(s1) != regs.check_any(s2)) + return regs.check_any(s2); + if (conns.check_any(s1) != conns.check_any(s2)) + return conns.check_any(s2); + } if (w1->port_output != w2->port_output) return w2->port_output; |