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author | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
commit | 288ba9618af9c5ba9db1131955c92d59166d120d (patch) | |
tree | d65852d388355322a9e7166ba0b0661e24eb220e | |
parent | 647c23b7b7e3a72fc64d9b1ad07dacd590865898 (diff) | |
download | yosys-288ba9618af9c5ba9db1131955c92d59166d120d.tar.gz yosys-288ba9618af9c5ba9db1131955c92d59166d120d.tar.bz2 yosys-288ba9618af9c5ba9db1131955c92d59166d120d.zip |
Moved common techlib files to techlibs/common
-rw-r--r-- | Makefile | 2 | ||||
-rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 | ||||
-rw-r--r-- | manual/CHAPTER_Techmap.tex | 2 | ||||
-rw-r--r-- | passes/techmap/Makefile.inc | 2 | ||||
-rw-r--r-- | techlibs/Makefile.inc | 7 | ||||
-rw-r--r-- | techlibs/common/Makefile.inc | 7 | ||||
-rw-r--r-- | techlibs/common/blackbox.sed (renamed from techlibs/blackbox.sed) | 0 | ||||
-rw-r--r-- | techlibs/common/simlib.v (renamed from techlibs/simlib.v) | 0 | ||||
-rw-r--r-- | techlibs/common/stdcells.v (renamed from techlibs/stdcells.v) | 0 | ||||
-rw-r--r-- | techlibs/common/stdcells_sim.v (renamed from techlibs/stdcells_sim.v) | 0 | ||||
-rwxr-xr-x | tests/i2c_bench/run-test.sh | 4 | ||||
-rwxr-xr-x | tests/tools/autotest.sh | 4 | ||||
-rwxr-xr-x | tests/tools/rtlview.sh | 2 |
13 files changed, 17 insertions, 17 deletions
@@ -73,7 +73,7 @@ endif include frontends/*/Makefile.inc include passes/*/Makefile.inc include backends/*/Makefile.inc -include techlibs/Makefile.inc +include techlibs/*/Makefile.inc top-all: $(TARGETS) $(EXTRA_TARGETS) diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index b4f988129..09be0870e 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -22,7 +22,7 @@ Note that all RTL cells have parameters indicating the size of inputs and output passes modify RTL cells they must always keep the values of these parameters in sync with the size of the signals connected to the inputs and outputs. -Simulation models for the RTL cells can be found in the file {\tt techlibs/simlib.v} in the Yosys +Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys source tree. \subsection{Unary Operators} @@ -347,7 +347,7 @@ Add a brief description of the {\tt \$fsm} cell type. For gate level logic networks, fixed function single bit cells are used that do not provide any parameters. -Simulation models for these cells can be found in the file {\tt techlibs/stdcells\_sim.v} in the Yosys +Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys source tree. \begin{table}[t] diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index 6a84864e2..be74c3567 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -27,7 +27,7 @@ cells with the provided implementation. When no map file is provided, {\tt techmap} uses a built-in map file that maps the Yosys RTL cell types to the internal gate library used by Yosys. -The curious reader may find this map file as {\tt techlibs/stdcells.v} in +The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in the Yosys source tree. Additional features have been added to {\tt techmap} to allow for conditional diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 970236259..152950663 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -2,7 +2,7 @@ GENFILES += passes/techmap/stdcells.inc OBJS += passes/techmap/techmap.o -passes/techmap/stdcells.inc: techlibs/stdcells.v +passes/techmap/stdcells.inc: techlibs/common/stdcells.v echo "// autogenerated from $<" > $@.new od -v -td1 -w1 $< | awk 'BEGIN { print "static char stdcells_code[] = {"; } $$2 != "" { print $$2 ","; } \ END { print 0 "};"; }' | fmt >> $@.new diff --git a/techlibs/Makefile.inc b/techlibs/Makefile.inc deleted file mode 100644 index 6c2a5f66a..000000000 --- a/techlibs/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ - -EXTRA_TARGETS += techlibs/blackbox.v - -techlibs/blackbox.v: techlibs/blackbox.sed techlibs/simlib.v techlibs/stdcells_sim.v - cat techlibs/simlib.v techlibs/stdcells_sim.v | sed -rf techlibs/blackbox.sed > techlibs/blackbox.v.new - mv techlibs/blackbox.v.new techlibs/blackbox.v - diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc new file mode 100644 index 000000000..ad0076456 --- /dev/null +++ b/techlibs/common/Makefile.inc @@ -0,0 +1,7 @@ + +EXTRA_TARGETS += techlibs/common/blackbox.v + +techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/stdcells_sim.v + cat techlibs/common/simlib.v techlibs/common/stdcells_sim.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new + mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v + diff --git a/techlibs/blackbox.sed b/techlibs/common/blackbox.sed index 4e9a3a7c6..4e9a3a7c6 100644 --- a/techlibs/blackbox.sed +++ b/techlibs/common/blackbox.sed diff --git a/techlibs/simlib.v b/techlibs/common/simlib.v index 7cd9906c9..7cd9906c9 100644 --- a/techlibs/simlib.v +++ b/techlibs/common/simlib.v diff --git a/techlibs/stdcells.v b/techlibs/common/stdcells.v index d861d796e..d861d796e 100644 --- a/techlibs/stdcells.v +++ b/techlibs/common/stdcells.v diff --git a/techlibs/stdcells_sim.v b/techlibs/common/stdcells_sim.v index 6e5d2719a..6e5d2719a 100644 --- a/techlibs/stdcells_sim.v +++ b/techlibs/common/stdcells_sim.v diff --git a/tests/i2c_bench/run-test.sh b/tests/i2c_bench/run-test.sh index 5fdbb0594..580ce4c0d 100755 --- a/tests/i2c_bench/run-test.sh +++ b/tests/i2c_bench/run-test.sh @@ -27,8 +27,8 @@ EOT ./testbench_ref -tclbatch testbench_ref.tcl vlogcomp --work syn i2c_master_syn.v -vlogcomp --work syn ../../techlibs/simlib.v -vlogcomp --work syn ../../techlibs/stdcells_sim.v +vlogcomp --work syn ../../techlibs/common/simlib.v +vlogcomp --work syn ../../techlibs/common/stdcells_sim.v vlogcomp --work syn i2c_slave_model.v vlogcomp --work syn spi_slave_model.v vlogcomp --work syn tst_bench_top.v diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index cb1e3a96d..992c8563e 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -130,8 +130,8 @@ do "$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v $libs \ - "$toolsdir"/../../techlibs/simlib.v \ - "$toolsdir"/../../techlibs/stdcells_sim.v + "$toolsdir"/../../techlibs/common/simlib.v \ + "$toolsdir"/../../techlibs/common/stdcells_sim.v if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count} test_count=$(( test_count + 1 )) diff --git a/tests/tools/rtlview.sh b/tests/tools/rtlview.sh index 6a4adcae1..61fef802e 100755 --- a/tests/tools/rtlview.sh +++ b/tests/tools/rtlview.sh @@ -11,7 +11,7 @@ prjdir="$(dirname $0)/rtlview.tmp" mkdir -p "$prjdir" cp "$1" "$prjdir"/schematic.v -cp "$(dirname $0)"/../../techlibs/blackbox.v "$prjdir"/blackbox.v +cp "$(dirname $0)"/../../techlibs/common/blackbox.v "$prjdir"/blackbox.v cd "$prjdir" if fuser -s ise.out; then |