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* Merge pull request #677 from daveshah1/ecp5_dspClifford Wolf2018-10-233-1/+97
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| * ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
| * ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | Merge pull request #674 from rubund/feature/svinterface_at_topClifford Wolf2018-10-2011-70/+599
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| * Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-204-136/+113
| * Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-209-10/+561
| * Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #673 from daveshah1/ecp5_improveClifford Wolf2018-10-194-6/+17
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| * ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
| * ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
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* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
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| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
* | Merge pull request #671 from rafaeltp/masterClifford Wolf2018-10-191-2/+3
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| * | adding offset info to memoriesrafaeltp2018-10-181-1/+1
| * | adding offset info to memoriesrafaeltp2018-10-181-2/+3
* | | Merge pull request #670 from rubund/feature/basic_svinterface_testClifford Wolf2018-10-196-9/+248
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| * | Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-186-9/+248
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* | Update ABC to git rev 14d985aClifford Wolf2018-10-181-1/+1
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-1811-21/+649
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| * | Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * | Documentation improvements etc.Ruben Undheim2018-10-135-38/+77
| * | Fix build error with clangRuben Undheim2018-10-121-1/+1
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-128-14/+121
| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-1210-21/+501
* | | Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
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| * | | xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
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* | | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
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| * | | ignore protect endprotectargama2018-10-161-0/+3
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* | | Update ABC to git rev c5b48bbClifford Wolf2018-10-171-1/+1
* | | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
* | | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
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| * | | detect ff/latch before processing other nodesargama2018-10-141-0/+17
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* | | Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
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| * | | Minor updateAman Goel2018-10-152-3/+3
| * | | Update to .smv backendAman Goel2018-10-012-35/+54
| * | | Merge pull request #4 from YosysHQ/masterAman Goel2018-10-0131-107/+529
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* | \ \ \ Merge pull request #658 from daveshah1/ecp5_bramClifford Wolf2018-10-179-20/+371
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| * | | | | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
| * | | | | BRAM improvementsDavid Shah2018-10-121-11/+16
| * | | | | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
| * | | | | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
| * | | | | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
| * | | | | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
| * | | | | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
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* | | | | Merge pull request #641 from tklam/masterClifford Wolf2018-10-171-0/+69
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| * | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
| * | | | | stop check_signal_in_fanout from traversing FFstklam2018-10-131-1/+12
| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-136-17/+61
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| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosystklam2018-10-034-7/+12
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