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| author | tklam <tklam@easylogic.hk> | 2018-10-13 23:24:24 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-10-13 23:24:24 +0800 |
| commit | f4343b3dc7dfb1908848b21b406f13884e8c407a (patch) | |
| tree | d03adc9ad6c833c51294d0c41ddc867ec9d64cfa | |
| parent | 302edf04291467469f8f48bd60edadbf1ee54798 (diff) | |
| download | yosys-f4343b3dc7dfb1908848b21b406f13884e8c407a.tar.gz yosys-f4343b3dc7dfb1908848b21b406f13884e8c407a.tar.bz2 yosys-f4343b3dc7dfb1908848b21b406f13884e8c407a.zip | |
stop check_signal_in_fanout from traversing FFs
| -rw-r--r-- | passes/equiv/equiv_make.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e75482e9f..66ee28aff 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -423,8 +423,8 @@ struct EquivMakeWorker auto driven_cells = bit2driven.at(source_bit); for (auto driven_cell: driven_cells) { - bool is_comb = comb_ct.cell_known(cell->type); - if (is_comb) + bool is_comb = comb_ct.cell_known(driven_cell->type); + if (!is_comb) continue; if (visited_cells.count(driven_cell) > 0) |