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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-10-08 16:52:12 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-10-08 16:52:12 -0700 |
| commit | b111ea12286b45e51fc453e3f4d7ac906e1a9f7c (patch) | |
| tree | ad9fcd28339318054214e2503518be94b936d4d3 | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.tar.gz yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.tar.bz2 yosys-b111ea12286b45e51fc453e3f4d7ac906e1a9f7c.zip | |
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 590fe61d2..b27c08529 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); if (vpr) - Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v"); - else - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut2lut.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } |