| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 10 | -21/+501 |
| * | Improve Verific importer blackbox handling | Clifford Wolf | 2018-10-07 | 1 | -2/+14 |
| * | Merge pull request #651 from ARandomOWL/stdcells_fix | Clifford Wolf | 2018-10-05 | 1 | -1/+1 |
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| | * | Fix IdString M in setup_stdcells() | Adrian Wheeldon | 2018-10-04 | 1 | -1/+1 |
| * | | Add "write_edif -attrprop" | Clifford Wolf | 2018-10-05 | 1 | -11/+28 |
| * | | Merge pull request #654 from mithro/patch-1 | Clifford Wolf | 2018-10-05 | 1 | -1/+1 |
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| | * | | Fix misspelling in issue_template.md | Tim Ansell | 2018-10-04 | 1 | -1/+1 |
| * | | | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-05 | 1 | -0/+2 |
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| * | | Add inout ports to cells_xtra.v | Clifford Wolf | 2018-10-04 | 2 | -2/+14 |
| * | | Merge pull request #650 from mithro/patch-1 | Clifford Wolf | 2018-10-04 | 1 | -0/+1 |
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| | * | | xilinx: Adding missing inout IO port to IOBUF | Tim Ansell | 2018-10-03 | 1 | -0/+1 |
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| * | | Merge pull request #645 from daveshah1/ecp5_dram_fix | Clifford Wolf | 2018-10-02 | 1 | -0/+1 |
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| | * | | ecp5: Don't map ROMs to DRAM | David Shah | 2018-10-01 | 1 | -0/+1 |
| * | | | Merge pull request #646 from tomverbeure/issue594 | Clifford Wolf | 2018-10-02 | 1 | -1/+2 |
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| | * | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 |
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| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| * | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| | * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
| * | | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-28 | 1 | -4/+4 |
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| | * | | Update to v2 YosysVS template | Clifford Wolf | 2018-09-28 | 1 | -4/+4 |
| * | | | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 |
| * | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
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| * | | Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc | Clifford Wolf | 2018-09-23 | 1 | -11/+11 |
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| | * | | added prefix to FDirection constants, fixing windows build | Miodrag Milanovic | 2018-09-21 | 1 | -11/+11 |
| * | | | Update CHANGELOG | Clifford Wolf | 2018-09-23 | 1 | -2/+35 |
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| * | | Update CHANGLELOG | Clifford Wolf | 2018-09-21 | 1 | -5/+27 |
| * | | Update Changelog | Clifford Wolf | 2018-09-21 | 1 | -1/+54 |
| * | | Merge pull request #633 from mmicko/master | Clifford Wolf | 2018-09-19 | 3 | -1/+14 |
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| | * | | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-09-19 | 3 | -1/+14 |
| * | | | Merge pull request #631 from acw1251/master | Clifford Wolf | 2018-09-19 | 2 | -5/+5 |
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| | * | | Fixed typo in "verilog_write" help message | acw1251 | 2018-09-18 | 2 | -5/+5 |
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| * | | Merge pull request #625 from aman-goel/master | Clifford Wolf | 2018-09-14 | 1 | -1/+7 |
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| | * | | Minor revision to -expose in setundef pass | Aman Goel | 2018-09-10 | 1 | -1/+7 |
| * | | | Merge pull request #627 from acw1251/master | Clifford Wolf | 2018-09-14 | 1 | -1/+1 |
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| | * | | | Fixed minor typo in "sim" help message | acw1251 | 2018-09-12 | 1 | -1/+1 |
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| * | / | Add iCE40 SB_SPRAM256KA simulation model | Clifford Wolf | 2018-09-10 | 1 | -9/+30 |
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| * | | Add $lut support to Verilog back-end | Clifford Wolf | 2018-09-06 | 1 | -0/+13 |
| * | | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 |
| * | | Add "make ystests" | Clifford Wolf | 2018-08-30 | 3 | -0/+10 |
| * | | Add GCC to osx deps (#620) | Miodrag Milanović | 2018-08-28 | 1 | -1/+1 |
| * | | Merge pull request #619 from mmicko/master | Clifford Wolf | 2018-08-28 | 2 | -6/+0 |
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| | * | | Remove mercurial, since it is not needed anymore | Miodrag Milanovic | 2018-08-28 | 2 | -6/+0 |
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| * | | Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes | Clifford Wolf | 2018-08-28 | 1 | -17/+112 |
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| | * \ | Merge branch 'master' into firrtl+modules+shiftfixes | Jim Lawson | 2018-08-27 | 12 | -39/+92 |
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| | | * \ | Merge pull request #3 from YosysHQ/master | Jim Lawson | 2018-08-27 | 12 | -39/+92 |
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| * | | | | Add "make coverage" | Clifford Wolf | 2018-08-27 | 8 | -13/+21 |
| * | | | | Add ENABLE_GCOV build option | Clifford Wolf | 2018-08-27 | 1 | -0/+11 |
| * | | | | Merge pull request #617 from mmicko/master | Clifford Wolf | 2018-08-25 | 1 | -1/+1 |
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| | * | | | | static link flag on main executable | Miodrag Milanovic | 2018-08-25 | 1 | -1/+1 |
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| * | | | | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
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