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* | Added -selected option to various backendsClifford Wolf2013-09-033-9/+58
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-224-0/+167
* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-221-13/+61
* Added edif backend (still under construction)Clifford Wolf2013-08-222-0/+202
* Merge pull request #10 from hansiglaser/masterClifford Wolf2013-08-211-0/+2
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| * fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-211-0/+2
* | Some minor documentation fixesClifford Wolf2013-08-212-2/+2
* | Merge pull request #9 from hansiglaser/masterClifford Wolf2013-08-203-4/+24
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| * Added support for include directories with the new '-I' argument of theJohann Glaser2013-08-203-4/+24
* | Merge pull request #8 from hansiglaser/masterClifford Wolf2013-08-202-4/+8
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| * Added support for notif0/notif1 primitivesJohann Glaser2013-08-202-4/+8
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* Added cleaning of old version_* files to version_* make ruleClifford Wolf2013-08-201-1/+2
* Added version info to yosys command and added -V optionClifford Wolf2013-08-203-2/+22
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-202-5/+5
* Fixed width and sign detection for ** operatorClifford Wolf2013-08-191-3/+3
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-192-33/+59
* Improved ast dumping (ast/verilog frontend)Clifford Wolf2013-08-194-64/+35
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-152-7/+59
* Fixed signed div/mod in const eval (rounding and stuff)Clifford Wolf2013-08-151-2/+8
* Added ezsat api for creation of anonymous vectorsClifford Wolf2013-08-152-0/+9
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-152-2/+17
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-152-9/+25
* Added support for "2**n" shifter encodingClifford Wolf2013-08-122-24/+33
* Added SAT support for $div and $mod cellsClifford Wolf2013-08-113-0/+55
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-112-4/+21
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-112-1/+7
* freduce performance fixClifford Wolf2013-08-101-4/+8
* Added $div and $mod technology mappingClifford Wolf2013-08-094-34/+137
* Added techmap -opt modeClifford Wolf2013-08-092-9/+44
* Some fixes to improve determinismClifford Wolf2013-08-095-32/+41
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-081-0/+3
* Added -try option to freduce passClifford Wolf2013-08-081-16/+44
* Added "clean" command (less verbose opt_clean)Clifford Wolf2013-08-081-9/+52
* Fixed topological ordering in freduce passClifford Wolf2013-08-071-54/+67
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-072-7/+39
* Added stubnets example to manual prog chapterClifford Wolf2013-08-073-7/+15
* Small bugfixes in freduce passClifford Wolf2013-08-061-4/+14
* Added freduce commandClifford Wolf2013-08-062-0/+362
* Fixed SigPool::del() methodClifford Wolf2013-08-061-1/+1
* Added proper deallocation of history bufferClifford Wolf2013-08-061-0/+5
* Updated TODO section in READMEClifford Wolf2013-08-011-9/+1
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-276-12/+246
* Added "help -write-web-command-reference-manual"Clifford Wolf2013-07-261-0/+52
* Fixed comments in manual rtlil/ilang syntaxClifford Wolf2013-07-251-2/+1
* Added RTLIL and Liberty syntax highlighting to manualClifford Wolf2013-07-253-4/+19
* Automatically run "proc" on extract map filesClifford Wolf2013-07-241-0/+5
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-237-28/+304
* Fixed "make clean" for manual filesClifford Wolf2013-07-231-1/+1
* Added web site link to READMEClifford Wolf2013-07-211-0/+8