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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-01 20:02:15 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-01 20:02:15 +0200 |
| commit | 8b2f7792ba7a1f4c42f6185a24bd49c6f6985863 (patch) | |
| tree | fc4d28078af9cad4121bc4ee88e259b7e5116dd0 | |
| parent | 0f38008ed34e36e798f521b4b6d4fea89ae31a3b (diff) | |
| download | yosys-8b2f7792ba7a1f4c42f6185a24bd49c6f6985863.tar.gz yosys-8b2f7792ba7a1f4c42f6185a24bd49c6f6985863.tar.bz2 yosys-8b2f7792ba7a1f4c42f6185a24bd49c6f6985863.zip | |
Updated TODO section in README
| -rw-r--r-- | README | 10 |
1 files changed, 1 insertions, 9 deletions
@@ -238,14 +238,6 @@ Verilog Attributes and non-standard features TODOs / Open Bugs ================= -- Write "design and implementation of.." document - - - Source tree layout - - Data formats (c++ classes, etc.) - - Internal misc. frameworks (log, select) - - Build system and pass registration - - Internal cell library - - Implement missing Verilog 2005 features: - Signed constants @@ -264,7 +256,7 @@ TODOs / Open Bugs - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - Add edit commands for changing the design (delete, add, modify objects) - Improve TCL support (add mechanism for inspecting the design from TCL) - - Additional internal cell types: $pla and $lut + - Add full support for $lut cell type (const evaluation, sat solving, etc.) - Support for registering designs (as collection of modules) to CellTypes - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) - Refactoring of AST frontend (clean expr width/sign code, AST passes) |