iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added API and Makefile rules for share/ files	Clifford Wolf	2013-10-27	4	-0/+26
*	Added design->full_selection() helper method	Clifford Wolf	2013-10-27	1	-0/+3
*	Moved simple xilinx counter sim example to subdir	Clifford Wolf	2013-10-27	3	-0/+0
*	Xilinx mojo_counter example is now working	Clifford Wolf	2013-10-27	3	-4/+9
*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27	1	-4/+4
*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26	8	-0/+0
*	Improved xilinx mojo_counter example	Clifford Wolf	2013-10-26	2	-2/+5
*	Added support for i/o buffers to iopadmap	Clifford Wolf	2013-10-26	1	-10/+35
*	Added another xilinx example (not funcional yet)	Clifford Wolf	2013-10-26	4	-0/+101
*	Added support for sr flip-flops to dfflibmap	Clifford Wolf	2013-10-24	1	-3/+168
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24	3	-17/+147
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	6	-8/+8
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24	6	-10/+10
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	5	-14/+29
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	3	-10/+22
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23	1	-1/+1
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21	2	-5/+99
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19	2	-8/+21
*	Changed NEW_WIRE API to return the wire, not the signal	Clifford Wolf	2013-10-18	2	-2/+2
*	Added dffsr support to proc_dff pass	Clifford Wolf	2013-10-18	1	-7/+72
*	Added RTLIL NEW_WIRE macro	Clifford Wolf	2013-10-18	2	-0/+13
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18	1	-0/+181
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	3	-0/+181
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	3	-49/+80
*	Improved way of connecting ports in techmap pass	Clifford Wolf	2013-10-17	1	-18/+36
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17	1	-5/+6
*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17	1	-2/+40
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17	1	-2/+7
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17	1	-3/+31
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17	1	-0/+3
*	Added iopadmap pass	Clifford Wolf	2013-10-16	4	-2/+167
*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16	6	-11/+10
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16	1	-2/+39
*	Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'	Clifford Wolf	2013-10-16	1	-1/+4
*	Added recommended apt-get commands to README	Clifford Wolf	2013-10-11	1	-2/+20
*	Fixed minisat include	Clifford Wolf	2013-10-11	1	-1/+1
*	Pinned ABC revision to 0f9e5488ced3	Clifford Wolf	2013-10-03	1	-1/+3
*	Improvements in EDIF backend	Clifford Wolf	2013-09-17	2	-2/+41
*	Added additional options to BLIF backend	Clifford Wolf	2013-09-15	1	-15/+60
*	Added BLIF backend	Clifford Wolf	2013-09-15	2	-0/+245
*	A couple of small fixes in SPICE backend	Clifford Wolf	2013-09-15	1	-6/+18
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	13	-17/+17
*	Updated manual	Clifford Wolf	2013-09-15	3	-21/+173
*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14	5	-6/+73
*	Added spice backend	Clifford Wolf	2013-09-14	6	-0/+306
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-09-03	2	-10/+41
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\| *	Encode large (>32 bits) parameters as hex string in edif backend	Clifford Wolf	2013-08-28	1	-3/+16
\| *	Improved edif backend	Clifford Wolf	2013-08-27	1	-8/+18
\| *	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	Clifford Wolf	2013-08-27	1	-2/+10