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| * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
| * | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
| * | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
| * | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
| * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | Updating gowinDiego H2019-09-022-2/+2
| * | | | | Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| * | | | | Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosysPepijn de Vos2019-09-043-5/+6
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| * | | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
* | | | | | | Fix #1462, #1480.Marcin Kościelnicki2019-11-194-9/+40
* | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
* | | | | | | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fixClifford Wolf2019-11-182-4/+21
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| * | | | | | | Fix #1496.Marcin Kościelnicki2019-11-182-4/+21
* | | | | | | | Merge pull request #1494 from whitequark/write_verilog-extmemwhitequark2019-11-181-10/+80
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| * | | | | | | write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
* | | | | | | | Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arstClifford Wolf2019-11-171-4/+10
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| * | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUEDavid Shah2019-11-141-4/+10
* | | | | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
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* | | | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-143-0/+136
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| * | | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-133-0/+136
* | | | | | | Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streamsClifford Wolf2019-11-141-6/+286
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| * \ \ \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python...Benedikt Tutzer2019-10-1525-61/+345
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| * | | | | | | | Fix renaming all classes to Cpp*Benedikt Tutzer2019-10-091-2/+2
| * | | | | | | | Expose global variables and allow logging to python streamsBenedikt Tutzer2019-10-091-6/+286
* | | | | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| * | | | | | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| * | | | | | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* | | | | | | | | | Merge branch 'makaimann-label-bads-btor'Clifford Wolf2019-11-141-1/+6
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| * | | | | | | | | | Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| * | | | | | | | | | Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into mak...Clifford Wolf2019-11-141-1/+10
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| * | | | | | | | | | Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
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* | | | | | | | | | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
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| * | | | | | | | | flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| * | | | | | | | | flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
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* | | | | | | | | Merge pull request #1486 from YosysHQ/clifford/fsmdetectfixClifford Wolf2019-11-131-6/+10
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| * | | | | | | | | Update fsm_detect bugfixClifford Wolf2019-11-121-3/+4
| * | | | | | | | | Bugfix in fsm_detectClifford Wolf2019-11-121-6/+9
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* | | | | | | | | Merge pull request #1484 from YosysHQ/clifford/cmp2luteqneClifford Wolf2019-11-126-18/+35
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| * | | | | | | | Fixed testsMiodrag Milanovic2019-11-115-17/+34
| * | | | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
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* | | | | | | | Merge pull request #1470 from YosysHQ/clifford/subpassdocClifford Wolf2019-11-101-0/+46
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| * | | | | | | | Add CodingReadme section on script passesClifford Wolf2019-10-311-0/+46
* | | | | | | | | Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
* | | | | | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
* | | | | | | | | Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
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* | | | | | | | Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
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| * | | | | | | | write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
* | | | | | | | | Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
* | | | | | | | | Merge pull request #1455 from YosysHQ/dave/ultrascaleplusDavid Shah2019-10-249-417/+1153
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