| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #2564 from whitequark/flatten-improve-error | whitequark | 2021-01-29 | 1 | -1/+1 |
| |\ | | | | | flatten: clarify confusing error message | ||||
| | * | flatten: clarify confusing error message. | whitequark | 2021-01-26 | 1 | -1/+1 |
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| * | | Bump version | Yosys Bot | 2021-01-29 | 1 | -1/+1 |
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| * | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces | whitequark | 2021-01-28 | 2 | -1/+25 |
| |\ \ | | | | | | | verilog: strip leading and trailing spaces in macro args | ||||
| | * | | verilog: strip leading and trailing spaces in macro args | Zachary Snow | 2021-01-28 | 2 | -1/+25 |
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| * | | | Merge pull request #2535 from Ravenslofty/scc-specify | Claire Xen | 2021-01-28 | 2 | -18/+61 |
| |\ \ \ | |/ / |/| | | scc: Add -specify option to find loops in boxes | ||||
| | * | | scc: Add -specify option to find loops in boxes | Dan Ravensloft | 2021-01-26 | 2 | -18/+61 |
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| * | | | Bump version | Yosys Bot | 2021-01-27 | 1 | -1/+1 |
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| * | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED. | Marcelina Kościelnicka | 2021-01-27 | 3 | -4/+51 |
| | | | | | | | | | | | | | | | | | | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559. | ||||
| * | | | xilinx: Add FDRSE_1, FDCPE_1. | Marcelina Kościelnicka | 2021-01-27 | 1 | -0/+80 |
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| * | | | Merge pull request #2563 from whitequark/cxxrtl-msvc | whitequark | 2021-01-26 | 2 | -10/+10 |
| |\ \ \ | | | | | | | | | cxxrtl: do not use `->template` for non-dependent names | ||||
| | * | | | cxxrtl: do not use `->template` for non-dependent names. | whitequark | 2021-01-26 | 2 | -10/+10 |
| | | |/ | |/| | | | | | | | This breaks build on MSVC but not GCC/Clang. | ||||
| * | | | Merge pull request #2544 from modwizcode/fix-clock | whitequark | 2021-01-26 | 1 | -7/+15 |
| |\ \ \ | |/ / |/| | | CXXRTL: Fix sliced bits as clock inputs | ||||
| | * | | Improves the previous commit with a more complete coverage of the cases | Iris Johnson | 2021-01-15 | 1 | -12/+12 |
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| | * | | Handle sliced bits as clock inputs (fixes #2542) | Iris Johnson | 2021-01-14 | 1 | -3/+11 |
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| * | | | Bump version | Yosys Bot | 2021-01-26 | 1 | -1/+1 |
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| * | | | Merge pull request #2549 from pgadfort/support-multiple-libs | whitequark | 2021-01-25 | 1 | -15/+21 |
| |\ \ \ | | | | | | | | | adding support for passing multiple liberty files to abc | ||||
| | * | | | adding support for passing multiple liberty files to abc | Peter Gadfort | 2021-01-18 | 1 | -15/+21 |
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| * | | | | Merge pull request #2550 from zachjs/macro-arg-spaces | whitequark | 2021-01-25 | 2 | -1/+28 |
| |\ \ \ \ | | | | | | | | | | | verilog: allow spaces in macro arguments | ||||
| | * | | | | verilog: allow spaces in macro arguments | Zachary Snow | 2021-01-20 | 2 | -1/+28 |
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| * | | | | Bump version | Yosys Bot | 2021-01-25 | 1 | -1/+1 |
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| * | | | | Merge pull request #2558 from YosysHQ/dave/chandle-dpi | Claire Xen | 2021-01-24 | 1 | -1/+16 |
| |\ \ \ \ | | | | | | | | | | | dpi: Support for chandle type | ||||
| | * | | | | dpi: Support for chandle type | David Shah | 2021-01-23 | 1 | -1/+16 |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | | Bump version | Yosys Bot | 2021-01-22 | 1 | -1/+1 |
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| * | | | | Merge pull request #2553 from zachjs/rand-const-modifiers | Miodrag Milanović | 2021-01-21 | 3 | -2/+19 |
| |\ \ \ \ | | | | | | | | | | | Allow combination of rand and const modifiers | ||||
| | * | | | | Allow combination of rand and const modifiers | Zachary Snow | 2021-01-21 | 3 | -2/+19 |
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| * | | | | Bump version | Yosys Bot | 2021-01-21 | 1 | -1/+1 |
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| * | | | | Merge pull request #2552 from YosysHQ/claire/yosyshq | Claire Xen | 2021-01-21 | 1 | -18/+18 |
| |\ \ \ \ | | | | | | | | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific | ||||
| | * | | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵ | Claire Xenia Wolf | 2021-01-20 | 1 | -18/+18 |
| |/ / / / | | | | | | | | | | | | | | | | | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | | | | Merge pull request #2536 from TobiasFaller/master | Miodrag Milanović | 2021-01-20 | 1 | -0/+1 |
| |\ \ \ \ | | | | | | | | | | | Fixed missing goto statement in passes/techmap/abc.cc | ||||
| | * | | | | Fixed missing goto statement in passes/techmap/abc.cc | Tobias Faller | 2021-01-12 | 1 | -0/+1 |
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| * | | | | Merge pull request #2551 from zachjs/wire-logic | Miodrag Milanović | 2021-01-20 | 3 | -9/+65 |
| |\ \ \ \ | |_|/ / |/| | | | sv: fix support wire and var data type modifiers | ||||
| | * | | | sv: fix support wire and var data type modifiers | Zachary Snow | 2021-01-20 | 3 | -9/+65 |
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| * | | | Bump version | Yosys Bot | 2021-01-19 | 1 | -1/+1 |
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| * | | | Merge pull request #2547 from zachjs/plugin-so-dsym | whitequark | 2021-01-18 | 1 | -0/+1 |
| |\ \ \ | | | | | | | | | Add plugin.so.dSYM to .gitignore | ||||
| | * | | | Add plugin.so.dSYM to .gitignore | Zachary Snow | 2021-01-18 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | This artifact is automatically generated by the builtin clang on macOS when -g is used. | ||||
| * | | | | Merge pull request #2312 from antmicro/typedef-inout | whitequark | 2021-01-18 | 4 | -30/+152 |
| |\ \ \ \ | |/ / / |/| | | | Add support for user types in IOs | ||||
| | * | | | Add typedef input/output test | Kamil Rakoczy | 2021-01-18 | 2 | -0/+117 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
| | * | | | Fix input/output attributes when resolving typedef of wire | Kamil Rakoczy | 2021-01-18 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
| | * | | | Parse package user type in module port list | Lukasz Dalek | 2021-01-18 | 1 | -30/+32 |
| |/ / / | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
| * | / | Bump version | Yosys Bot | 2021-01-15 | 1 | -1/+1 |
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| * | | opt_share: Fix X and CO signal width for shifted $alu in opt_share. | Marcelina Kościelnicka | 2021-01-14 | 2 | -2/+22 |
| | | | | | | | | | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538. | ||||
| * | | Bump version | Yosys Bot | 2021-01-14 | 1 | -1/+1 |
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| * | | Merge pull request #2537 from pepijndevos/spice | Claire Xen | 2021-01-13 | 1 | -7/+15 |
| |\ \ | |/ |/| | Add buffer option to spice backend | ||||
| | * | add buffer option to spice backend | Pepijn de Vos | 2021-01-13 | 1 | -7/+15 |
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| * | Bump version | Yosys Bot | 2021-01-05 | 1 | -1/+1 |
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| * | Merge pull request #2522 from tomverbeure/simlib_typos2 | whitequark | 2021-01-04 | 1 | -5/+5 |
| |\ | | | | | Fix some trivial typos. | ||||
| | * | Fix some trivial typos. | Tom Verbeure | 2021-01-03 | 1 | -5/+5 |
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| * | Bump version | Yosys Bot | 2021-01-02 | 1 | -1/+1 |
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| * | Merge pull request #2480 from YosysHQ/dave/nexus-lram | whitequark | 2021-01-01 | 5 | -1/+227 |
| |\ | | | | | nexus: Add LRAM inference | ||||
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index : iCE40/yosys | |
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