diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-01-14 09:58:33 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-01-14 14:54:08 +0100 |
| commit | 01626e6746e85832d5b75785b9e45f39ff8eb299 (patch) | |
| tree | e32c1fcb601b283525d38bab8d1d2861f45e9118 | |
| parent | 7cd044bbc4cc4b63302363f77d913403957fdcd3 (diff) | |
| download | yosys-01626e6746e85832d5b75785b9e45f39ff8eb299.tar.gz yosys-01626e6746e85832d5b75785b9e45f39ff8eb299.tar.bz2 yosys-01626e6746e85832d5b75785b9e45f39ff8eb299.zip | |
opt_share: Fix X and CO signal width for shifted $alu in opt_share.
These need to be the same length as actual Y, not visible part of Y.
Fixes #2538.
| -rw-r--r-- | passes/opt/opt_share.cc | 4 | ||||
| -rw-r--r-- | tests/opt/opt_share_bug2538.ys | 20 |
2 files changed, 22 insertions, 2 deletions
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 53296699c..62a478673 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -244,8 +244,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< } if (shared_op->type.in(ID($alu))) { - shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out))); - shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out))); + shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out))); + shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys new file mode 100644 index 000000000..7261c6695 --- /dev/null +++ b/tests/opt/opt_share_bug2538.ys @@ -0,0 +1,20 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A; +input S; +output [1:0] Y; + +wire [3:0] A1 = A + 1; +wire [3:0] A2 = A + 2; +assign Y = S ? A1[3:2] : A2[3:2]; + +endmodule + +EOT + +proc +alumacc +equiv_opt -assert opt_share + |