| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | | | Copy attributes to _TECHMAP_REPLACE_ cells | Clifford Wolf | 2017-02-16 | 1 | -2/+8 | |
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| * | | | | | | | | Fix eval implementation of $_NOR_ | Clifford Wolf | 2017-02-16 | 1 | -1/+1 | |
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| * | | | | | | | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 | |
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| * | | | | | | | Add warning about x/z bits left unconnected in EDIF output | Clifford Wolf | 2017-02-14 | 1 | -2/+5 | |
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| * | | | | | | | Fix double-call of log_pop() in synth_greenpak4 | Clifford Wolf | 2017-02-14 | 1 | -2/+0 | |
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| * | | | | | | | Merge pull request #313 from azidar/bugfix-assign-wmask | Clifford Wolf | 2017-02-14 | 3 | -27/+181 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | More progress on Firrtl backend. | |||||
| | * | | | | | | | More progress on Firrtl backend. | Adam Izraelevitz | 2017-02-13 | 3 | -27/+181 | |
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a simple rocket-chip design. | |||||
| * | | | | | | | Do not fix port widths on any blackbox instances | Clifford Wolf | 2017-02-13 | 1 | -1/+1 | |
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| * | | | | | | | Fix techmap for inout ports connected to inout ports | Clifford Wolf | 2017-02-13 | 1 | -2/+7 | |
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| * | | | | | | | Do not eagerly fix port widths on parameterized cells | Clifford Wolf | 2017-02-12 | 1 | -0/+3 | |
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| * | | | | | | | Add "yosys -w" for suppressing warnings | Clifford Wolf | 2017-02-12 | 3 | -11/+34 | |
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| * | | | | | | Add support for verific mem initialization | Clifford Wolf | 2017-02-11 | 1 | -0/+38 | |
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| * | | | | | | Fix another stupid bug in the same line | Clifford Wolf | 2017-02-11 | 1 | -1/+1 | |
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| * | | | | | | Add verific support for initialized variables | Clifford Wolf | 2017-02-11 | 1 | -3/+47 | |
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| * | | | | | | Improve handling of Verific warnings and error messages | Clifford Wolf | 2017-02-11 | 1 | -4/+10 | |
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| * | | | | | | Fix extremely stupid typo | Clifford Wolf | 2017-02-11 | 1 | -1/+1 | |
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| * | | | | | | Add log_wire() API | Clifford Wolf | 2017-02-11 | 2 | -0/+8 | |
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| * | | | | | | Fixed some "used uninitialized" warnings in opt_expr | Clifford Wolf | 2017-02-11 | 1 | -1/+2 | |
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| * | | | | | | Evaluate all the $(shell ...) stuff for CXXFLAGS et al only once | Clifford Wolf | 2017-02-11 | 1 | -3/+3 | |
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| * | | | | | | Merge branch 'stv0g-master' | Clifford Wolf | 2017-02-11 | 2 | -21/+40 | |
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| | * | | | | | | Make MacOS Makefile stuff more compact | Clifford Wolf | 2017-02-11 | 1 | -8/+0 | |
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| | * | | | | | | Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master | Clifford Wolf | 2017-02-11 | 2 | -21/+48 | |
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| | * | | | | | | Use pkg-config for linking tcl-tk | Steffen Vogel | 2017-02-10 | 1 | -3/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both MacPorts and Homebrew have a pkg-config file for TCL. So lets use it. | |||||
| | * | | | | | | Dont mix Homebrew and MacPorts build options | Steffen Vogel | 2017-02-10 | 1 | -2/+1 | |
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| | * | | | | | | Remove space after backslash | Steffen Vogel | 2017-02-09 | 1 | -1/+1 | |
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| | * | | | | | | Applied fixes from @joshhead (thanks for your effors!) | Steffen Vogel | 2017-02-09 | 2 | -5/+7 | |
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| | * | | | | | | Added notes for compilation on OS X | Steffen Vogel | 2017-02-07 | 1 | -3/+13 | |
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| | * | | | | | | Fix compilation on OS X in order to support both MacPorts and Homebrew | Steffen Vogel | 2017-02-07 | 1 | -13/+25 | |
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| | * | | | | | | Allow standard tools to be overwritten in make invocation | Steffen Vogel | 2017-02-07 | 1 | -3/+3 | |
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| | * | | | | | | use Homebrew only if installed | Steffen Vogel | 2017-01-31 | 1 | -6/+8 | |
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| * | | | | | | | Add optimization of (a && 1'b1) and (a || 1'b0) | Clifford Wolf | 2017-02-11 | 1 | -7/+22 | |
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| * | | | | | | | Merge pull request #308 from C-Elegans/opt_compare_fix_pr | Clifford Wolf | 2017-02-11 | 1 | -1/+19 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | Fix issue #306, "Bug in opt -full" | |||||
| | * | | | | | | | Fix issue #306, "Bug in opt -full" | C-Elegans | 2017-02-10 | 1 | -1/+19 | |
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0 | |||||
| * | | | | | | | Fix handling of init attributes with strange width | Clifford Wolf | 2017-02-09 | 2 | -3/+9 | |
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| * | | | | | | | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 3 | -14/+33 | |
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| * | | | | | | | Add "rand" and "rand const" verific support | Clifford Wolf | 2017-02-09 | 1 | -0/+41 | |
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| * | | | | | | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 3 | -10/+33 | |
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| * | | | | | | Add PSL parser mode to verific front-end | Clifford Wolf | 2017-02-08 | 1 | -2/+17 | |
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| * | | | | | | Add "read_blif -wideports" | Clifford Wolf | 2017-02-06 | 2 | -5/+77 | |
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| * | | | | | | Fix undef propagation bug in $pmux SAT model | Clifford Wolf | 2017-02-05 | 1 | -14/+4 | |
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| * | | | | | | Update ABC to hg rev a2fcd1cc61a6 | Clifford Wolf | 2017-02-05 | 1 | -1/+1 | |
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| * | | | | | | Merge pull request #304 from esden/gsed-darwin | Clifford Wolf | 2017-02-05 | 1 | -1/+1 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | Use gsed vs sed on Darwin. | |||||
| | * | | | | | | Use -E sed parameter instead of -r. | Piotr Esden-Tempski | 2017-02-04 | 1 | -1/+1 | |
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | BSD sed equivalent to -r parameter is -E and it is also supported in GNU sed thus using -E results in support on both platforms. | |||||
| * | | | | | | Add assert check in "yosys-smtbmc -c" | Clifford Wolf | 2017-02-04 | 1 | -7/+28 | |
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| * | | | | | | Improve yosys-smtbmc cover() support | Clifford Wolf | 2017-02-04 | 1 | -5/+19 | |
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| * | | | | | | Partially implement cover() support in yosys-smtbmc | Clifford Wolf | 2017-02-04 | 3 | -4/+97 | |
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| * | | | | | | Further improve cover() support | Clifford Wolf | 2017-02-04 | 3 | -8/+16 | |
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| * | | | | | | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 14 | -9/+38 | |
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| * | | | | | | Add assert/assume support to verific front-end | Clifford Wolf | 2017-02-04 | 2 | -625/+687 | |
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| * | | | | | | Update ABC to hg rev fe96921e5d50 | Clifford Wolf | 2017-02-01 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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