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* Bugfix in RTLIL::SigSpec::remove2()Clifford Wolf2016-12-311-3/+4
* Updated ABC to hg id 8c6a635f7a20Clifford Wolf2016-12-291-1/+1
* Improved write_json help messageClifford Wolf2016-12-291-0/+4
* Updated ABC to hg id f591c081d5e7Clifford Wolf2016-12-261-1/+1
* Merge pull request #284 from azonenberg/masterClifford Wolf2016-12-246-65/+328
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| * Merge pull request #1 from azonenberg-hk/masterAndrew Zonenberg2016-12-2319-70/+586
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| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-235-4/+44
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* | | Simplified log_spacer() codeClifford Wolf2016-12-231-6/+2
* | | Added "yosys -W regex"Clifford Wolf2016-12-223-2/+44
* | | Added AIGER back-end to automatic back-end detectionClifford Wolf2016-12-211-0/+2
* | | Updated ABC to hg rev a4872e22c646Clifford Wolf2016-12-211-1/+1
* | | Updated ABC to hg rev 8bab2eedbba4Clifford Wolf2016-12-211-1/+1
| | * greenpak4: Added INT pin to GP_SPIAndrew Zonenberg2016-12-211-1/+3
| | * greenpak4: removed unused MISO pin from GP_SPIAndrew Zonenberg2016-12-211-1/+0
| | * greenpak4: Removed SPI_BUFFER parameterAndrew Zonenberg2016-12-201-1/+0
| | * greenpak4: replaced MOSI/MISO with single one-way SDAT pinAndrew Zonenberg2016-12-201-2/+1
| | * greenpak4: Changed port names on GP_SPI for clarityAndrew Zonenberg2016-12-201-4/+4
| | * greenpak4: Initial implementation of GP_SPI cellAndrew Zonenberg2016-12-201-0/+27
| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-172-1/+61
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* | | Added "verilog_defines" commandClifford Wolf2016-12-151-0/+60
* | | Bugfix in comment handlingClifford Wolf2016-12-131-1/+1
| | * greenpak4: Updated GP_DCMP cell modelAndrew Zonenberg2016-12-171-2/+20
| | * greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.Andrew Zonenberg2016-12-161-5/+10
| | * greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed inte...Andrew Zonenberg2016-12-151-5/+24
| | * greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
| | * greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
| | * greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-127-0/+153
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* | | Added $anyconst support to AIGER back-endClifford Wolf2016-12-111-0/+7
* | | Merge branch 'LSS-USP-unit-test-structure'Clifford Wolf2016-12-116-0/+146
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| * | Some minor CodingReadme changes in unit test sectionClifford Wolf2016-12-111-10/+4
| * | Build hotfix in tests/unit/MakefileClifford Wolf2016-12-111-1/+1
| * | Improved unit test structurerodrigosiqueira2016-12-103-16/+20
| * | Added explanation about configure and create testrodrigosiqueira2016-12-041-0/+75
| * | Added required structure to implement unit testsrodrigosiqueira2016-12-045-0/+73
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| * Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
| * greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
| * greenpak4: Can now techmap inferred D latches (without set/reset or output in...Andrew Zonenberg2016-12-103-0/+17
| * greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...Andrew Zonenberg2016-12-101-15/+15
| * Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
| * Initial implementation of techlib support for GreenPAK latches. Instantiation...Andrew Zonenberg2016-12-052-0/+120
| * Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
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* Added $assert/$assume support to AIGER back-endClifford Wolf2016-12-033-13/+54
* Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aigClifford Wolf2016-12-031-2/+15
* Updated ABV to hg rev 8b555d9e67cfClifford Wolf2016-12-011-1/+1
* Added examples/aiger/Clifford Wolf2016-12-014-0/+53
* Added "yosys-smtbmc --aig"Clifford Wolf2016-12-011-6/+127
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