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* Support various binary operators in opt_shareBogdan Vukobratovic2019-08-045-194/+519
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* Tabs to spaces in opt_share examplesBogdan Vukobratovic2019-08-0310-150/+150
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* Fix spacing in opt_share tests, change wording in opt_share helpBogdan Vukobratovic2019-08-0311-161/+160
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* Reimplement opt_share to work on $alu and $pmuxBogdan Vukobratovic2019-07-2821-112/+520
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* Implement opt_shareBogdan Vukobratovic2019-07-266-1/+383
| | | | | | This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands
* Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-2517-29/+360
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| * Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.
| * | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
| |\ \ | | | | | | | | intel: Make -noiopads the default
| | * | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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| * | | Merge pull request #1219 from jakobwenzel/objIteratorClifford Wolf2019-07-252-3/+20
| |\ \ \ | | | | | | | | | | made ObjectIterator comply with Iterator Interface
| | * | | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
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| | * | | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-242-2/+19
| | |/ / | | | | | | | | | | | | this makes it possible to use std algorithms on them
| * | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
| |\ \ \ | | | | | | | | | | xilinx: Fix missing cell name underscore in cells_map.v
| | * | | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | Merge pull request #1222 from koriakin/s6-exampleEddie Hung2019-07-245-0/+47
| |\ \ \ \ | | |_|/ / | |/| | | Add a simple example for Spartan 6
| | * | | Add a simple example for Spartan 6Marcin Kościelnicki2019-07-245-0/+47
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| * | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dspEddie Hung2019-07-233-9/+241
| |\ \ \ | | | | | | | | | | ice40: Fix SB_MAC16 sim model for signed modes
| | * | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
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| | * | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
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| * | | | Merge pull request #1214 from jakobwenzel/astmod_cloneEddie Hung2019-07-221-0/+2
| |\ \ \ \ | | |_|_|/ | |/| | | initialize noblackbox and nowb in AstModule::clone
| | * | | initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
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| * / / Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / / Bump abc to fix &mfs bugEddie Hung2019-07-251-1/+1
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* | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
|\ \ | | | | | | Assorted synth_intel cleanups from @bwidawsk
| * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
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| * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
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| * | synth_intel: revert change to run_max10Dan Ravensloft2019-07-181-1/+1
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| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-182-29/+11
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | Merge pull request #1207 from ZirconiumX/intel_new_pass_namesDavid Shah2019-07-181-4/+4
|\ \ \ | |/ / |/| | synth_intel: rename for consistency with #1184
| * | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
|/ / | | | | | | Also fix a typo in the help message.
* | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
|\ \ | | | | | | synth_{ice40,ecp5}: more sensible pass label naming
| * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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* | | Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
|\ \ \ | | | | | | | | write_verilog: dump zero width constants correctly
| * | | write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
* | | | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
|\ \ \ \ | |/ / / |/| | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #1202 from YosysHQ/cmp2lut_lut6Eddie Hung2019-07-164-24/+37
|\ \ \ | |/ / |/| | cmp2lut transformation to support >32 bit LUT masks
| * | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | Forgot to commitEddie Hung2019-07-161-0/+7
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| * | Add tests for cmp2lut on LUT6Eddie Hung2019-07-162-23/+29
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* | Merge pull request #1188 from YosysHQ/eddie/abc9_push_invertersEddie Hung2019-07-162-45/+128
|\ \ | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
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