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| | * greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
| | * greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
| | * greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
| | * greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
| | * Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-12-127-0/+153
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* | | Added $anyconst support to AIGER back-endClifford Wolf2016-12-111-0/+7
* | | Merge branch 'LSS-USP-unit-test-structure'Clifford Wolf2016-12-116-0/+146
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| * | Some minor CodingReadme changes in unit test sectionClifford Wolf2016-12-111-10/+4
| * | Build hotfix in tests/unit/MakefileClifford Wolf2016-12-111-1/+1
| * | Improved unit test structurerodrigosiqueira2016-12-103-16/+20
| * | Added explanation about configure and create testrodrigosiqueira2016-12-041-0/+75
| * | Added required structure to implement unit testsrodrigosiqueira2016-12-045-0/+73
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| * Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
| * greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
| * greenpak4: Can now techmap inferred D latches (without set/reset or output in...Andrew Zonenberg2016-12-103-0/+17
| * greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...Andrew Zonenberg2016-12-101-15/+15
| * Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
| * Initial implementation of techlib support for GreenPAK latches. Instantiation...Andrew Zonenberg2016-12-052-0/+120
| * Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
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* Added $assert/$assume support to AIGER back-endClifford Wolf2016-12-033-13/+54
* Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aigClifford Wolf2016-12-031-2/+15
* Updated ABV to hg rev 8b555d9e67cfClifford Wolf2016-12-011-1/+1
* Added examples/aiger/Clifford Wolf2016-12-014-0/+53
* Added "yosys-smtbmc --aig"Clifford Wolf2016-12-011-6/+127
* Added support for partially initialized regs to smt2 back-endClifford Wolf2016-12-011-3/+15
* Added "write_aiger -zinit -symbols -vmap"Clifford Wolf2016-12-011-30/+139
* Added "write_aiger" commandClifford Wolf2016-11-302-0/+398
* Added "design -reset-vlog"Clifford Wolf2016-11-301-7/+32
* Improved equiv_purge log outputClifford Wolf2016-11-291-1/+1
* Bugfix in smt2 back-end for pure checker modulesClifford Wolf2016-11-281-0/+4
* Added support for macros as include file namesClifford Wolf2016-11-281-0/+2
* Bugfix in "read_verilog -D NAME=VAL" handlingClifford Wolf2016-11-281-3/+3
* Removed shebang line from smtio.py, fixes #279Clifford Wolf2016-11-271-1/+0
* Added wire start_offset and upto handling BLIF back-endClifford Wolf2016-11-231-1/+1
* Added wire start_offset and upto handling to splitnets cmdClifford Wolf2016-11-231-2/+8
* Merge pull request #274 from oldtopman/lcursesClifford Wolf2016-11-221-0/+5
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| * Added optional flag for linking curses with readline.oldtopman2016-11-211-0/+5
* | Added "yosys-smtbmc --append"Clifford Wolf2016-11-221-2/+20
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* Merge pull request #272 from AlexDaniel/masterClifford Wolf2016-11-191-63/+64
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| * Keep lines under 80 charactersAleks-Daniel Jakimenko-Aleksejev2016-11-191-10/+11
| * Markdownify README even furtherAleks-Daniel Jakimenko-Aleksejev2016-11-191-60/+60
* | Improved ABC default scriptsClifford Wolf2016-11-191-17/+34
* | Merge pull request #271 from azidar/bugfix-assign-wmaskClifford Wolf2016-11-191-0/+1
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| * Bugfix: include assign to write-maskAdam Izraelevitz2016-11-181-0/+1
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* More progress in FIRRTL back-endClifford Wolf2016-11-183-4/+121
* Progress in FIRRTL back-endClifford Wolf2016-11-184-5/+55
* Added first draft of FIRRTL back-endClifford Wolf2016-11-172-0/+353
* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
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