| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 | |
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| | | * | | | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 | |
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| | | * | | | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 | |
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| | | * | | | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 | |
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| | * | | | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 9 | -3/+93 | |
| | |\ \ \ | | | | | | | | | | | elaboration system tasks | |||||
| | | * | | | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 4 | -50/+38 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 10 | -5/+107 | |
| | | |\ \ \ | | | | | | | | | | | | | | | | | | | clifford/pr983 | |||||
| | | | * | | | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 10 | -5/+107 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | |||||
| | * | | | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 | |
| | |/ / / / | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | Merge branch 'tux3-implicit_named_connection' | Clifford Wolf | 2019-06-07 | 4 | -3/+40 | |
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| | | * | | | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 3 | -13/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵ | Clifford Wolf | 2019-06-07 | 5 | -4/+52 | |
| | | |\ \ \ \ | | | |_|/ / | | |/| | | | | | | | | | into tux3-implicit_named_connection | |||||
| | | | * | | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 5 | -12/+59 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | |||||
| | * | | | | | Merge pull request #1076 from thasti/centos7-build-fix | Clifford Wolf | 2019-06-07 | 1 | -1/+0 | |
| | |\ \ \ \ \ | | |/ / / / | |/| | | | | Fix pyosys-build on CentOS7 | |||||
| | | * | | | | remove boost/log/exceptions.hpp from wrapper generator | Stefan Biereigel | 2019-06-07 | 1 | -1/+0 | |
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| * | | | | | Comment O(N) -> O(N^2) | Eddie Hung | 2019-06-07 | 1 | -1/+1 | |
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| * | | | | | Add nonexcl case test, comment out two others | Eddie Hung | 2019-06-07 | 2 | -22/+57 | |
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| * | | | | | Extend ExclusiveDatabase to query SigSpec-s (for $pmux) | Eddie Hung | 2019-06-07 | 1 | -19/+27 | |
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| * | | | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results | Eddie Hung | 2019-06-07 | 1 | -1/+64 | |
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| * | | | | | Add @cliffordwolf freduce testcase | Eddie Hung | 2019-06-07 | 2 | -0/+30 | |
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| * | | | | | Add nonexclusive test from @cliffordwolf | Eddie Hung | 2019-06-07 | 2 | -0/+28 | |
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| * | | | | | Resolve @cliffordwolf comment on redundant check | Eddie Hung | 2019-06-07 | 1 | -10/+2 | |
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| * | | | | | Resolve @cliffordwolf comment on sigmap | Eddie Hung | 2019-06-07 | 1 | -2/+2 | |
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| * | | | | | Another muxpack test | Eddie Hung | 2019-06-07 | 2 | -0/+32 | |
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| * | | | | | Fix and test for balanced case | Eddie Hung | 2019-06-06 | 3 | -10/+55 | |
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| * | | | | | Fix warnings | Eddie Hung | 2019-06-06 | 2 | -3/+3 | |
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| * | | | | | Support cascading $pmux.A with $mux.A and $mux.B | Eddie Hung | 2019-06-06 | 3 | -17/+65 | |
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| * | | | | | More cleanup | Eddie Hung | 2019-06-06 | 1 | -15/+20 | |
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| * | | | | | Fix spacing | Eddie Hung | 2019-06-06 | 1 | -6/+5 | |
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| * | | | | | Non chain user check using next_sig | Eddie Hung | 2019-06-06 | 1 | -7/+5 | |
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| * | | | | | Add non exclusive test | Eddie Hung | 2019-06-06 | 2 | -0/+56 | |
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| * | | | | | Move muxpack from passes/techmap to passes/opt | Eddie Hung | 2019-06-06 | 3 | -1/+1 | |
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| * | | | | | Update doc | Eddie Hung | 2019-06-06 | 1 | -4/+5 | |
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| * | | | | | Add to CHANGELOG | Eddie Hung | 2019-06-06 | 1 | -0/+1 | |
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| * | | | | | One more and tidy up | Eddie Hung | 2019-06-06 | 2 | -6/+28 | |
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| * | | | | | Add a few more special case tests | Eddie Hung | 2019-06-06 | 2 | -0/+51 | |
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| * | | | | | Add tests, fix for != | Eddie Hung | 2019-06-06 | 3 | -9/+110 | |
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| * | | | | | Missing file | Eddie Hung | 2019-06-06 | 1 | -0/+232 | |
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| * | | | | | Initial adaptation of muxpack from shregmap | Eddie Hung | 2019-06-06 | 1 | -0/+1 | |
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| * | | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 14 | -10/+279 | |
| |\ \ \ \ | | | | | | | | | | | Added support for parsing attributes on port connections. | |||||
| | * | | | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | * | | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵ | Maciej Kurc | 2019-06-04 | 4 | -0/+46 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | * | | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| | * | | | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | |||||
| * | | | | | Merge pull request #1073 from whitequark/ecp5-diamond-iob | David Shah | 2019-06-06 | 1 | -0/+15 | |
| |\ \ \ \ \ | | | | | | | | | | | | | ECP5: implement most Diamond I/O buffer primitives | |||||
| | * | | | | | ECP5: implement all Diamond I/O buffer primitives. | whitequark | 2019-06-06 | 1 | -0/+15 | |
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| * | | | | | | Merge pull request #1071 from YosysHQ/eddie/fix_1070 | Clifford Wolf | 2019-06-06 | 1 | -2/+2 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | Fix typo in opt_rmdff causing register to be incorrectly removed | |||||
| | * | | | | | | Fix typo in opt_rmdff | Eddie Hung | 2019-06-05 | 1 | -2/+2 | |
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| * | | | | | | | Merge pull request #1072 from YosysHQ/eddie/fix_1069 | Clifford Wolf | 2019-06-06 | 1 | -0/+5 | |
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | Error out if no top module given before 'sim' | |||||
| | * | | | | | | | Error out if no top module given before 'sim' | Eddie Hung | 2019-06-05 | 1 | -0/+5 | |
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index : iCE40/yosys | |
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