| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | Update LUT7/8 delays to take account for [ABC]OUTMUX delay | Eddie Hung | 2019-06-17 | 1 | -5/+5 | |
| * | | | | &scorr before &sweep, remove &retime as recommended | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
| * | | | | Copy not move parameters/attributes | Eddie Hung | 2019-06-17 | 1 | -3/+4 | |
| * | | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 3 | -27/+37 | |
| * | | | | Try -W 300 | Eddie Hung | 2019-06-17 | 1 | -1/+2 | |
| * | | | | Re-enable &dc2 | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
| * | | | | Cleanup | Eddie Hung | 2019-06-16 | 3 | -299/+33 | |
| * | | | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O | Eddie Hung | 2019-06-15 | 1 | -2/+2 | |
| * | | | | Leave breadcrumb behind | Eddie Hung | 2019-06-14 | 1 | -0/+2 | |
| * | | | | Remove redundant condition | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
| * | | | | Revert "Cleanup/optimise toposort in write_xaiger" | Eddie Hung | 2019-06-14 | 1 | -44/+40 | |
| * | | | | Update comment | Eddie Hung | 2019-06-14 | 1 | -1/+2 | |
| * | | | | Check that whiteboxes are synthesisable | Eddie Hung | 2019-06-14 | 1 | -4/+8 | |
| * | | | | Get rid of compiler warnings | Eddie Hung | 2019-06-14 | 2 | -7/+7 | |
| * | | | | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 | |
| * | | | | Cover __APPLE__ too for little to big endian | Eddie Hung | 2019-06-14 | 2 | -8/+16 | |
| * | | | | Update abc9 -D doc | Eddie Hung | 2019-06-14 | 1 | -1/+2 | |
| * | | | | Enable "abc9 -D <num>" for timing-driven synthesis | Eddie Hung | 2019-06-14 | 1 | -9/+9 | |
| * | | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 4 | -47/+47 | |
| * | | | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 3 | -17/+11 | |
| * | | | | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 | |
| * | | | | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 | |
| * | | | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 | |
| * | | | | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
| * | | | | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 5 | -79/+79 | |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-14 | 2 | -0/+46 | |
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| | * | | | Merge pull request #829 from abdelrahmanhosny/master | Serge Bazanski | 2019-06-13 | 2 | -0/+46 | |
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| | | * | | address review comments | Abdelrahman | 2019-03-01 | 1 | -23/+9 | |
| | | * | | add dockerignore file | Abdelrahman | 2019-02-26 | 1 | -0/+13 | |
| | | * | | dockerize yosys | Abdelrahman | 2019-02-26 | 1 | -0/+47 | |
| * | | | | Make doc consistent | Eddie Hung | 2019-06-14 | 3 | -3/+6 | |
| * | | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -1/+0 | |
| * | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-14 | 8 | -72/+194 | |
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| | * \ \ \ | Merge pull request #1097 from YosysHQ/dave/xaig_ecp5 | Eddie Hung | 2019-06-14 | 8 | -72/+194 | |
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| | | * | | | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 8 | -72/+194 | |
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| * | | | | | Cleanup | Eddie Hung | 2019-06-14 | 1 | -7/+3 | |
| * | | | | | Cleanup/optimise toposort in write_xaiger | Eddie Hung | 2019-06-14 | 1 | -54/+47 | |
| * | | | | | Remove extra semicolon | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
| * | | | | | Add TODO to parse_xaiger | Eddie Hung | 2019-06-14 | 1 | -0/+1 | |
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| * | | | | Optimise some more | Eddie Hung | 2019-06-13 | 1 | -58/+53 | |
| * | | | | Move ConstEvalAig to aigerparse.cc | Eddie Hung | 2019-06-13 | 2 | -160/+161 | |
| * | | | | Fix name clash | Eddie Hung | 2019-06-13 | 1 | -4/+8 | |
| * | | | | More slimming | Eddie Hung | 2019-06-13 | 1 | -35/+35 | |
| * | | | | Add ConstEvalAig specialised for AIGs | Eddie Hung | 2019-06-13 | 2 | -3/+159 | |
| * | | | | Update CHANGELOG with "synth -abc9" | Eddie Hung | 2019-06-13 | 1 | -0/+1 | |
| * | | | | Fix LP SB_LUT4 timing | Eddie Hung | 2019-06-13 | 1 | -1/+1 | |
| * | | | | More accurate CHANGELOG | Eddie Hung | 2019-06-13 | 1 | -1/+3 | |
| * | | | | Update CHANGELOG | Eddie Hung | 2019-06-12 | 1 | -0/+1 | |
| * | | | | Rip out all non FPGA stuff from abc9 | Eddie Hung | 2019-06-12 | 1 | -343/+111 | |
| * | | | | Fix spelling | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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