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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:10:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:10:46 -0700 |
| commit | 746f70a9ce163f921b0e55b21042c59769bbcba9 (patch) | |
| tree | eeba01979d6bc2e530834ee05fabccf49cdeaa22 | |
| parent | 0fa6a441f1a222b039975cf622ddca479a65cf24 (diff) | |
| download | yosys-746f70a9ce163f921b0e55b21042c59769bbcba9.tar.gz yosys-746f70a9ce163f921b0e55b21042c59769bbcba9.tar.bz2 yosys-746f70a9ce163f921b0e55b21042c59769bbcba9.zip | |
Update comment
| -rw-r--r-- | backends/aiger/xaiger.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bc722e492..0c2ae62e6 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -822,7 +822,8 @@ struct XAigerWriter Pass::call(holes_module->design, "flatten -wb"); - // TODO: Should techmap/AIG all lib_whitebox-es once + // TODO: Should techmap/aigmap/check all lib_whitebox-es just once, + // instead of per write_xaiger call Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "aigmap"); for (auto cell : holes_module->cells()) |