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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-032-3/+62
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| * Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-031-0/+57
| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-031-3/+5
* | Fixed detectSignWidthWorker (ast frontend) for AST_CONCATClifford Wolf2013-11-031-1/+1
* | Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...Clifford Wolf2013-11-023-8/+12
* | Added roadmap to readme fileClifford Wolf2013-11-021-0/+9
* | Various ast changes for early expression width detection (prep for constfold ...Clifford Wolf2013-11-025-30/+146
* | Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-312-0/+26
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-313-4/+4
* | Changed MiniSAT feater defines againClifford Wolf2013-10-311-2/+3
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* Added paragraph to README file to avoid mycells.lib confusionClifford Wolf2013-10-311-0/+3
* README file typo fixClifford Wolf2013-10-311-1/+1
* Some additions to the README fileClifford Wolf2013-10-311-0/+19
* Fixed ezminisat C++ errors: undef PRIi64Clifford Wolf2013-10-301-1/+2
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-301-4/+15
* Fixed help message typo (memory pass)Clifford Wolf2013-10-301-1/+1
* Added -format option to splitnetsClifford Wolf2013-10-291-1/+16
* Merge pull request #12 from jameswalmsley/masterClifford Wolf2013-10-274-0/+56
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| * [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-274-0/+56
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* Fixed get_share_file_name() for installed yosysClifford Wolf2013-10-271-2/+3
* Cleanups in xilinx examplesClifford Wolf2013-10-273-144/+28
* Added synth_xilinx commandClifford Wolf2013-10-272-0/+219
* Added API and Makefile rules for share/ filesClifford Wolf2013-10-274-0/+26
* Added design->full_selection() helper methodClifford Wolf2013-10-271-0/+3
* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-273-0/+0
* Xilinx mojo_counter example is now workingClifford Wolf2013-10-273-4/+9
* Fixed hex string generation bug in edif backendClifford Wolf2013-10-271-4/+4
* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-268-0/+0
* Improved xilinx mojo_counter exampleClifford Wolf2013-10-262-2/+5
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-261-10/+35
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-264-0/+101
* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-241-3/+168
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-243-17/+147
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-246-8/+8
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-246-10/+10
* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-245-14/+29
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-243-10/+22
* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-231-1/+1
* Improved handling of dff with async resetsClifford Wolf2013-10-212-5/+99
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-192-8/+21
* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-182-2/+2
* Added dffsr support to proc_dff passClifford Wolf2013-10-181-7/+72
* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-182-0/+13
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-181-8/+8
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-181-0/+181
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-183-0/+181
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-183-49/+80
* Improved way of connecting ports in techmap passClifford Wolf2013-10-171-18/+36
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-171-5/+6
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-171-2/+40