iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Provide an integer implementation of decimal_digits().	Henner Zeller	2021-02-01	1	-2/+9
*	Fix digit-formatting calculation for small numbers.	Henner Zeller	2021-01-21	1	-6/+10
*	Merge pull request #2553 from zachjs/rand-const-modifiers	Miodrag Milanović	2021-01-21	3	-2/+19
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\| *	Allow combination of rand and const modifiers	Zachary Snow	2021-01-21	3	-2/+19
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*	Bump version	Yosys Bot	2021-01-21	1	-1/+1
*	Merge pull request #2552 from YosysHQ/claire/yosyshq	Claire Xen	2021-01-21	1	-18/+18
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\| *	Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavor...	Claire Xenia Wolf	2021-01-20	1	-18/+18
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*	Merge pull request #2536 from TobiasFaller/master	Miodrag Milanović	2021-01-20	1	-0/+1
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\| *	Fixed missing goto statement in passes/techmap/abc.cc	Tobias Faller	2021-01-12	1	-0/+1
* \|	Merge pull request #2551 from zachjs/wire-logic	Miodrag Milanović	2021-01-20	3	-9/+65
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\| * \|	sv: fix support wire and var data type modifiers	Zachary Snow	2021-01-20	3	-9/+65
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* \|	Bump version	Yosys Bot	2021-01-19	1	-1/+1
* \|	Merge pull request #2547 from zachjs/plugin-so-dsym	whitequark	2021-01-18	1	-0/+1
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\| * \|	Add plugin.so.dSYM to .gitignore	Zachary Snow	2021-01-18	1	-0/+1
* \| \|	Merge pull request #2312 from antmicro/typedef-inout	whitequark	2021-01-18	4	-30/+152
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\| * \|	Add typedef input/output test	Kamil Rakoczy	2021-01-18	2	-0/+117
\| * \|	Fix input/output attributes when resolving typedef of wire	Kamil Rakoczy	2021-01-18	1	-0/+3
\| * \|	Parse package user type in module port list	Lukasz Dalek	2021-01-18	1	-30/+32
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* \|	Bump version	Yosys Bot	2021-01-15	1	-1/+1
* \|	opt_share: Fix X and CO signal width for shifted $alu in opt_share.	Marcelina Kościelnicka	2021-01-14	2	-2/+22
* \|	Bump version	Yosys Bot	2021-01-14	1	-1/+1
* \|	Merge pull request #2537 from pepijndevos/spice	Claire Xen	2021-01-13	1	-7/+15
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\| *	add buffer option to spice backend	Pepijn de Vos	2021-01-13	1	-7/+15
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*	Bump version	Yosys Bot	2021-01-05	1	-1/+1
*	Merge pull request #2522 from tomverbeure/simlib_typos2	whitequark	2021-01-04	1	-5/+5
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\| *	Fix some trivial typos.	Tom Verbeure	2021-01-03	1	-5/+5
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*	Bump version	Yosys Bot	2021-01-02	1	-1/+1
*	Merge pull request #2480 from YosysHQ/dave/nexus-lram	whitequark	2021-01-01	5	-1/+227
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\| *	nexus: Add LRAM inference	David Shah	2020-12-07	5	-1/+227
* \|	Merge pull request #2512 from umarcor/plugin-err	whitequark	2021-01-01	1	-1/+5
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\| * \|	plugin: enhance no-plugin error	umarcor	2020-12-29	1	-1/+5
* \| \|	Merge pull request #2515 from umarcor/fix/ghdl	whitequark	2021-01-01	1	-2/+2
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\| * \| \|	makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX	umarcor	2020-12-30	1	-2/+2
* \| \| \|	Merge pull request #2518 from zachjs/recursion	whitequark	2021-01-01	4	-8/+99
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\| * \| \| \|	verilog: improved support for recursive functions	Zachary Snow	2020-12-31	4	-8/+99
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* \| \| \|	Merge pull request #2517 from zachjs/sv-tf-implied-direction	whitequark	2021-01-01	3	-0/+39
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\| * \| \|	sv: complete support for implied task/function port directions	Zachary Snow	2020-12-31	3	-0/+39
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* / /	Bump version	Yosys Bot	2020-12-30	1	-1/+1
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* \|	Merge pull request #2509 from zachjs/issue-2427	whitequark	2020-12-29	4	-1/+56
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\| * \|	Fix elaboration of whole memory words used as indices	Zachary Snow	2020-12-26	4	-1/+56
* \| \|	Merge pull request #2514 from umarcor/feat/ghdl	whitequark	2020-12-29	1	-0/+9
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\| * \| \|	makefile: add support for built-in ghdl-yosys-plugin	umarcor	2020-12-28	1	-0/+9
* \| \| \|	Bump version	Yosys Bot	2020-12-29	1	-1/+1
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* \| \|	Merge pull request #2511 from umarcor/feat/msys2-32	whitequark	2020-12-28	1	-5/+7
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\| * \| \|	makefile: rename msys2 to msys2-32, config PREFIX	umarcor	2020-12-28	1	-5/+7
* \| \| \|	Merge pull request #2507 from umarcor/fix/msys2	whitequark	2020-12-28	1	-2/+3
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\| * \| \|	kernel/yosys.h: undef CONST on WIN32	umarcor	2020-12-28	1	-2/+3
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* \| \|	Bump version	Yosys Bot	2020-12-28	1	-1/+1
* \| \|	Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast	Claire Xen	2020-12-27	1	-0/+3
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\| * \|	CODEOWNERS: add @zachjs as Verilog/AST frontend owner	whitequark	2020-12-27	1	-0/+3
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