| Commit message (Expand) | Author | Age | Files | Lines |
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| * | machxo2: Add -noiopad option to synth_machxo2. | William D. Jones | 2021-02-23 | 1 | -2/+11 |
| * | machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| * | machxo2: Fix cells_sim typo where OFX1 was multiply-driven. | William D. Jones | 2021-02-23 | 1 | -1/+1 |
| * | machxo2: synth_machxo2 now maps ports to FACADE_IO. | William D. Jones | 2021-02-23 | 2 | -0/+12 |
| * | machxo2: Add initial value for Q in FACADE_FF. | William D. Jones | 2021-02-23 | 1 | -0/+2 |
| * | machxo2: Add FACADE_IO simulation model. More comments on models. | William D. Jones | 2021-02-23 | 1 | -0/+25 |
| * | machxo2: Add FACADE_SLICE simulation model. | William D. Jones | 2021-02-23 | 1 | -0/+83 |
| * | machxo2: Improve FACADE_FF simulation model. | William D. Jones | 2021-02-23 | 1 | -12/+20 |
| * | machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. | William D. Jones | 2021-02-23 | 2 | -4/+4 |
| * | machxo2: Add dffe test. | William D. Jones | 2021-02-23 | 1 | -0/+9 |
| * | machxo2: Add dff.ys test, fix another cells_map.v typo. | William D. Jones | 2021-02-23 | 2 | -1/+11 |
| * | machxo2: Fix more oversights in machxo2 models. logic.ys test passes. | William D. Jones | 2021-02-23 | 2 | -2/+6 |
| * | machxo2: Add test/arch/machxo2 directory (test does not pass). | William D. Jones | 2021-02-23 | 4 | -0/+15 |
| * | machxo2: Fix typos. test/arch/run-test.sh passes. | William D. Jones | 2021-02-23 | 2 | -2/+2 |
| * | machxo2: Create basic techlibs and synth_machxo2 pass. | William D. Jones | 2021-02-23 | 4 | -0/+320 |
| * | frontend: json: parse negative values | Karol Gugala | 2021-02-23 | 1 | -2/+10 |
| * | assertpmux: Fix crash on unused $pmux output. | Marcelina Kościelnicka | 2021-02-22 | 2 | -1/+19 |
| * | Merge pull request #2586 from zachjs/tern-recurse | whitequark | 2021-02-21 | 5 | -19/+195 |
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| | * | verilog: support recursive functions using ternary expressions | Zachary Snow | 2021-02-12 | 5 | -19/+195 |
| * | | Merge pull request #2591 from zachjs/verilog-preproc-unapplied | whitequark | 2021-02-21 | 3 | -1/+32 |
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| | * | | verilog: error on macro invocations with missing argument lists | Zachary Snow | 2021-02-19 | 3 | -1/+32 |
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| * | | Bump version | Yosys Bot | 2021-02-18 | 1 | -1/+1 |
| * | | Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode | Claire Xen | 2021-02-17 | 1 | -1/+1 |
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| | * | | Fixes command line for abc pass in -fast -sop mode | Robert Baruch | 2021-02-16 | 1 | -1/+1 |
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| * | | Bump version | Yosys Bot | 2021-02-16 | 1 | -1/+1 |
| * | | Merge pull request #2574 from dh73/master | Claire Xen | 2021-02-15 | 1 | -0/+5 |
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| | * | | Accept disable case for SVA liveness properties. | Diego H | 2021-02-04 | 1 | -0/+5 |
| * | | | Bump version | Yosys Bot | 2021-02-13 | 1 | -1/+1 |
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| * | | Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct | gatecat | 2021-02-12 | 1 | -0/+115 |
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| | * | | nexus: Add MULTADDSUB9X9WIDE sim model | David Shah | 2020-12-08 | 1 | -0/+115 |
| * | | | Ganulate Verific support | Miodrag Milanovic | 2021-02-12 | 1 | -8/+16 |
| * | | | Bump version | Yosys Bot | 2021-02-12 | 1 | -1/+1 |
| * | | | Merge pull request #2573 from zachjs/repeat-call | whitequark | 2021-02-11 | 4 | -72/+176 |
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| | * | | | verilog: refactored constant function evaluation | Zachary Snow | 2021-02-04 | 4 | -72/+176 |
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| * | | | Merge pull request #2578 from zachjs/genblk-port | Zachary Snow | 2021-02-11 | 3 | -4/+29 |
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| | * | | | verlog: allow shadowing module ports within generate blocks | Zachary Snow | 2021-02-07 | 3 | -4/+29 |
| * | | | | Merge pull request #2584 from antmicro/atom_type_signedness | Zachary Snow | 2021-02-11 | 2 | -4/+23 |
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| | * | | | Add missing is_signed to type_atom | Kamil Rakoczy | 2021-02-11 | 2 | -4/+23 |
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| * | | | Bump version | Yosys Bot | 2021-02-07 | 1 | -1/+1 |
| * | | | Merge pull request #2576 from zachjs/port-bind-sign-uniop | whitequark | 2021-02-06 | 3 | -8/+33 |
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| | * | | | genrtlil: fix signed port connection codegen failures | Zachary Snow | 2021-02-05 | 3 | -8/+33 |
| * | | | | Bump version | Yosys Bot | 2021-02-06 | 1 | -1/+1 |
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| * | | | Merge pull request #2572 from antmicro/check-labels | whitequark | 2021-02-05 | 2 | -0/+28 |
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| | * | | | Add check of begin/end labels for genblock | Kamil Rakoczy | 2021-02-04 | 2 | -0/+28 |
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| * / / | Bump version | Yosys Bot | 2021-02-05 | 1 | -1/+1 |
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| * | | Merge pull request #2529 from zachjs/unnamed-genblk | whitequark | 2021-02-04 | 33 | -258/+779 |
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| | * | | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 33 | -258/+779 |
| * | | | Bump version | Yosys Bot | 2021-02-04 | 1 | -1/+1 |
| * | | | Merge pull request #2436 from dalance/fix_generate | whitequark | 2021-02-03 | 2 | -7/+4 |
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| | * | | | Fix begin/end in generate | dalance | 2020-11-11 | 2 | -7/+4 |
