Commit message (Expand) | Author | Age | Files | Lines | |
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* | Check other regex parameters | Miodrag Milanovic | 2020-02-22 | 1 | -15/+30 |
* | check for regex errors | Miodrag Milanovic | 2020-02-20 | 1 | -16/+20 |
* | Prevent double error message | Miodrag Milanovic | 2020-02-17 | 1 | -1/+3 |
* | Option to expect no warnings | Miodrag Milanovic | 2020-02-17 | 4 | -0/+12 |
* | Add to changelog | Miodrag Milanovic | 2020-02-17 | 1 | -0/+1 |
* | No new error if already failing | Miodrag Milanovic | 2020-02-17 | 1 | -1/+2 |
* | remove whitespace | Miodrag Milanovic | 2020-02-14 | 1 | -1/+1 |
* | Add expect option to logger command | Miodrag Milanovic | 2020-02-14 | 4 | -3/+113 |
* | Add new logger pass | Miodrag Milanovic | 2020-02-13 | 2 | -0/+142 |
* | abc9: cleanup | Eddie Hung | 2020-02-10 | 2 | -41/+41 |
* | Merge pull request #1670 from rodrigomelo9/master | Eddie Hung | 2020-02-10 | 7 | -3/+152 |
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| * | Added 'set -e' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -0/+20 |
| * | Modified $readmem[hb] to use '\' or '/' according the OS | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -1/+6 |
| * | Merge branch 'master' into master | Rodrigo A. Melo | 2020-02-03 | 10 | -4/+367 |
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| * \ | Merge branch 'master' of https://github.com/YosysHQ/yosys | Rodrigo Alejandro Melo | 2020-02-03 | 12 | -112/+369 |
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| * | | | Replaced strlen by GetSize into simplify.cc | Rodrigo Alejandro Melo | 2020-02-03 | 1 | -2/+2 |
| * | | | Removed 'synth' into tests/memfile/run-test.sh | Rodrigo Alejandro Melo | 2020-02-02 | 1 | -8/+8 |
| * | | | Added content1.dat into tests/memfile | Rodrigo Alejandro Melo | 2020-02-02 | 2 | -21/+81 |
| * | | | Removed a line jump into the CHANGELOG | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -3/+2 |
| * | | | Added tests/memfile to 'make test' with an extra testcase | Rodrigo Alejandro Melo | 2020-02-01 | 2 | -16/+11 |
| * | | | Added a test for the Memory Content File inclusion using $readmemb | Rodrigo Alejandro Melo | 2020-02-01 | 3 | -0/+63 |
| * | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is provided | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -1/+1 |
| * | | | Modified the new search for files of $readmem[hb] to be backward compatible | Rodrigo Alejandro Melo | 2020-01-31 | 1 | -3/+7 |
| * | | | $readmem[hb] file inclusion is now relative to the Verilog file | Rodrigo Alejandro Melo | 2020-01-31 | 2 | -2/+4 |
* | | | | Merge pull request #1669 from thasti/pyosys-attrs | N. Engelhardt | 2020-02-10 | 1 | -2/+38 |
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| * | | | | remove namespace mention from inheritance information | Stefan Biereigel | 2020-02-03 | 1 | -1/+1 |
| * | | | | expose polymorphism through python wrappers | Stefan Biereigel | 2020-02-03 | 1 | -2/+8 |
| * | | | | add inheritance for pywrap generators | Stefan Biereigel | 2020-01-30 | 1 | -0/+30 |
* | | | | | Merge pull request #1695 from whitequark/manual-explain-wire-upto-offset | whitequark | 2020-02-09 | 1 | -0/+7 |
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| * | | | | | manual: explain RTLIL::Wire::{upto,offset}. | whitequark | 2020-02-09 | 1 | -0/+7 |
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* | | | | | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 |
* | | | | | Merge pull request #1687 from YosysHQ/eddie/fix_ystests | Eddie Hung | 2020-02-07 | 2 | -9/+7 |
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| * | | | | | techmap: fix shiftx2mux decomposition | Eddie Hung | 2020-02-07 | 1 | -8/+6 |
| * | | | | | Fix misc.abc9.abc9_abc9_luts | Eddie Hung | 2020-02-07 | 1 | -1/+1 |
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* | | | | | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 5 | -27/+42 |
* | | | | | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 6 | -54/+235 |
* | | | | | Merge pull request #1685 from dh73/gowin | Eddie Hung | 2020-02-06 | 1 | -1/+1 |
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| * | | | | | Removing cells_sim.v from bram techmap pass | Diego H | 2020-02-06 | 1 | -1/+1 |
* | | | | | | Merge pull request #1683 from whitequark/write_verilog-memattrs | whitequark | 2020-02-07 | 1 | -0/+1 |
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| * | | | | | | write_verilog: dump $mem cell attributes. | whitequark | 2020-02-06 | 1 | -0/+1 |
* | | | | | | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 11 | -1/+370 |
* | | | | | | | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+39 |
* | | | | | | | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map | Eddie Hung | 2020-02-06 | 1 | -109/+43 |
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| * | | | | | | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 |
| * | | | | | | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 |
* | | | | | | | edif: more resilience to mismatched port connection sizes. | Marcin Kościelnicki | 2020-02-06 | 1 | -16/+27 |
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* | | | | | | Merge pull request #1682 from YosysHQ/eddie/opt_after_techmap | Eddie Hung | 2020-02-05 | 8 | -5/+9 |
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| * | | | | | | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 8 | -5/+9 |
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* / / / / / | shiftx2mux: fix select out of bounds | Eddie Hung | 2020-02-05 | 3 | -2/+14 |
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* | | | | | Merge pull request #1576 from YosysHQ/eddie/opt_merge_init | Eddie Hung | 2020-02-05 | 2 | -1/+65 |
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