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| author | whitequark <whitequark@whitequark.org> | 2020-02-07 02:54:04 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-07 02:54:04 +0000 |
| commit | 6f67dd8df52e6640f216661ae929cd3ed29d23cf (patch) | |
| tree | 1946dc0375c091f6781f9d287a6dc4c18dc50047 | |
| parent | 30854b9c7f23e2817a445761022668d6b0f7c0ef (diff) | |
| parent | e95a8ba763999b9cce480a3aadf9fae206650f00 (diff) | |
| download | yosys-6f67dd8df52e6640f216661ae929cd3ed29d23cf.tar.gz yosys-6f67dd8df52e6640f216661ae929cd3ed29d23cf.tar.bz2 yosys-6f67dd8df52e6640f216661ae929cd3ed29d23cf.zip | |
Merge pull request #1683 from whitequark/write_verilog-memattrs
write_verilog: dump $mem cell attributes
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 54d0f6148..682c47a1f 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // initial begin // memid[0] = ... // end + dump_attributes(f, indent.c_str(), cell->attributes); f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset); if (use_init) { |