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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2020-01-31 18:20:22 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2020-01-31 18:20:22 -0300 |
| commit | 7b3fe404ab30767a8b65f61fa2a6eebbe9019641 (patch) | |
| tree | 5498675a1b64bfe88e7c5a06e9d52b8a54eff31f | |
| parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
| download | yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.tar.gz yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.tar.bz2 yosys-7b3fe404ab30767a8b65f61fa2a6eebbe9019641.zip | |
$readmem[hb] file inclusion is now relative to the Verilog file
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| -rw-r--r-- | CHANGELOG | 3 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 3 |
2 files changed, 4 insertions, 2 deletions
@@ -53,12 +53,13 @@ Yosys 0.9 .. Yosys 0.9-dev - Added support for flip-flops with synchronous reset to synth_xilinx - Added support for flip-flops with reset and enable to synth_xilinx - Added "check -mapped" - - Added checking of SystemVerilog always block types (always_comb, + - Added checking of SystemVerilog always block types (always_comb, always_latch and always_ff) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - Added "abc9 -dff" - Added "synth_xilinx -dff" + - Improved support of $readmem[hb] file inclusion which is now relative to the Verilog file Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b94a8d710..f7364b9a8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2886,7 +2886,8 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m int meminit_size=0; std::ifstream f; - f.open(mem_filename.c_str()); + std::string path = filename.substr(0, filename.find_last_of("\\/")+1); + f.open(path + mem_filename.c_str()); yosys_input_files.insert(mem_filename); if (f.fail()) |