index
:
iCE40/yosys
master
clone of https://github.com/YosysHQ/yosys
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
*
Merge branch 'master' into eddie/muxpack
Eddie Hung
2019-06-07
39
-364
/
+573
|
\
|
*
Fix spacing from spaces to tabs
Eddie Hung
2019-06-07
1
-362
/
+362
|
*
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger
Clifford Wolf
2019-06-07
27
-45
/
+128
|
|
\
|
|
*
Add read_aiger to CHANGELOG
Eddie Hung
2019-06-07
1
-0
/
+1
|
|
*
Fix spacing (entire file is wrong anyway, will fix later)
Eddie Hung
2019-06-07
1
-3
/
+3
|
|
*
Remove unnecessary std::getline() for ASCII
Eddie Hung
2019-06-07
1
-3
/
+0
|
|
*
Test *.aag too, by using *.aig as reference
Eddie Hung
2019-06-07
1
-0
/
+19
|
|
*
Fix read_aiger -- create zero driver, fix init width, parse 'b'
Eddie Hung
2019-06-07
2
-13
/
+52
|
|
*
Use ABC to convert from AIGER to Verilog
Eddie Hung
2019-06-07
1
-2
/
+3
|
|
*
Use ABC to convert AIGER to Verilog, then sat against Yosys
Eddie Hung
2019-06-07
1
-21
/
+15
|
|
*
Add symbols to AIGER test inputs for ABC
Eddie Hung
2019-06-07
22
-8
/
+40
|
|
/
|
*
Merge pull request #1077 from YosysHQ/clifford/pr983
Clifford Wolf
2019-06-07
9
-3
/
+93
|
|
\
|
|
*
Fixes and cleanups in AST_TECALL handling
Clifford Wolf
2019-06-07
4
-50
/
+38
|
|
*
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
10
-5
/
+107
|
|
|
\
|
|
|
*
Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
10
-5
/
+107
|
*
|
|
Rename implicit_ports.sv test to implicit_ports.v
Clifford Wolf
2019-06-07
1
-0
/
+0
|
|
/
/
|
*
|
Merge branch 'tux3-implicit_named_connection'
Clifford Wolf
2019-06-07
4
-3
/
+40
|
|
\
\
|
|
*
|
Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
3
-13
/
+2
|
|
*
|
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
5
-4
/
+52
|
|
|
\
\
|
|
|
*
|
SystemVerilog support for implicit named port connections
tux3
2019-06-06
5
-12
/
+59
|
*
|
|
|
Merge pull request #1076 from thasti/centos7-build-fix
Clifford Wolf
2019-06-07
1
-1
/
+0
|
|
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
|
*
|
|
remove boost/log/exceptions.hpp from wrapper generator
Stefan Biereigel
2019-06-07
1
-1
/
+0
|
|
/
/
/
*
|
|
|
Comment O(N) -> O(N^2)
Eddie Hung
2019-06-07
1
-1
/
+1
*
|
|
|
Add nonexcl case test, comment out two others
Eddie Hung
2019-06-07
2
-22
/
+57
*
|
|
|
Extend ExclusiveDatabase to query SigSpec-s (for $pmux)
Eddie Hung
2019-06-07
1
-19
/
+27
*
|
|
|
Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results
Eddie Hung
2019-06-07
1
-1
/
+64
*
|
|
|
Add @cliffordwolf freduce testcase
Eddie Hung
2019-06-07
2
-0
/
+30
*
|
|
|
Add nonexclusive test from @cliffordwolf
Eddie Hung
2019-06-07
2
-0
/
+28
*
|
|
|
Resolve @cliffordwolf comment on redundant check
Eddie Hung
2019-06-07
1
-10
/
+2
*
|
|
|
Resolve @cliffordwolf comment on sigmap
Eddie Hung
2019-06-07
1
-2
/
+2
*
|
|
|
Another muxpack test
Eddie Hung
2019-06-07
2
-0
/
+32
*
|
|
|
Fix and test for balanced case
Eddie Hung
2019-06-06
3
-10
/
+55
*
|
|
|
Fix warnings
Eddie Hung
2019-06-06
2
-3
/
+3
*
|
|
|
Support cascading $pmux.A with $mux.A and $mux.B
Eddie Hung
2019-06-06
3
-17
/
+65
*
|
|
|
More cleanup
Eddie Hung
2019-06-06
1
-15
/
+20
*
|
|
|
Fix spacing
Eddie Hung
2019-06-06
1
-6
/
+5
*
|
|
|
Non chain user check using next_sig
Eddie Hung
2019-06-06
1
-7
/
+5
*
|
|
|
Add non exclusive test
Eddie Hung
2019-06-06
2
-0
/
+56
*
|
|
|
Move muxpack from passes/techmap to passes/opt
Eddie Hung
2019-06-06
3
-1
/
+1
*
|
|
|
Update doc
Eddie Hung
2019-06-06
1
-4
/
+5
*
|
|
|
Add to CHANGELOG
Eddie Hung
2019-06-06
1
-0
/
+1
*
|
|
|
One more and tidy up
Eddie Hung
2019-06-06
2
-6
/
+28
*
|
|
|
Add a few more special case tests
Eddie Hung
2019-06-06
2
-0
/
+51
*
|
|
|
Add tests, fix for !=
Eddie Hung
2019-06-06
3
-9
/
+110
*
|
|
|
Missing file
Eddie Hung
2019-06-06
1
-0
/
+232
*
|
|
|
Initial adaptation of muxpack from shregmap
Eddie Hung
2019-06-06
1
-0
/
+1
|
/
/
/
*
|
|
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
Clifford Wolf
2019-06-06
14
-10
/
+279
|
\
\
\
|
*
|
|
Fixed memory leak.
Maciej Kurc
2019-06-05
1
-0
/
+4
|
*
|
|
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ...
Maciej Kurc
2019-06-04
4
-0
/
+46
|
*
|
|
Added tests for attributes
Maciej Kurc
2019-06-03
9
-0
/
+219
[next]
