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* Fix first testcase in #1391Eddie Hung2019-09-202-2/+2
* Merge pull request #1386 from YosysHQ/clifford/fix1360Clifford Wolf2019-09-202-18/+30
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| * Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #...Clifford Wolf2019-09-202-18/+30
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* Update CHANGELOGClifford Wolf2019-09-201-0/+2
* Add "add -mod"Clifford Wolf2019-09-201-0/+18
* Merge pull request #1384 from YosysHQ/clifford/fix1381Clifford Wolf2019-09-201-5/+49
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| * Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
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* Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
* Added extractinv passMarcin Kościelnicki2019-09-195-0/+172
* Document (* gentb_skip *) attr for test_autotbEddie Hung2019-09-181-0/+3
* Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxextEddie Hung2019-09-186-14/+291
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| * OopsEddie Hung2019-09-131-1/+1
| * Add counter-example from @cliffordwolfEddie Hung2019-09-131-0/+24
| * Revert "Make one check $shift(x)? only; change testcase to be 8b"Eddie Hung2019-09-132-5/+4
| * Tidy upEddie Hung2019-09-111-10/+16
| * Fix UBEddie Hung2019-09-111-2/+2
| * Cope with presence of reset muxes tooEddie Hung2019-09-112-4/+64
| * CleanupEddie Hung2019-09-111-25/+22
| * Add more testsEddie Hung2019-09-111-0/+32
| * Only display log message if did_somethingEddie Hung2019-09-111-1/+1
| * Rename dffmuxext -> dffmux, also remove constants in dff+muxEddie Hung2019-09-114-57/+91
| * proc instead of prepEddie Hung2019-09-111-2/+2
| * Add unsigned caseEddie Hung2019-09-111-0/+17
| * Missing equiv_opt -assertEddie Hung2019-09-061-1/+1
| * Make one check $shift(x)? only; change testcase to be 8bEddie Hung2019-09-062-4/+5
| * Usee equiv_opt -assertEddie Hung2019-09-061-3/+3
| * simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-052-21/+63
| * Revert "abc9 followed by clean otherwise netlist could be invalid for sim"Eddie Hung2019-09-051-1/+0
| * Revert "parse_xaiger() to do "clean -purge""Eddie Hung2019-09-041-1/+1
| * abc9 followed by clean otherwise netlist could be invalid for simEddie Hung2019-09-041-0/+1
| * Remove log_cell() callsEddie Hung2019-09-041-3/+0
| * Add peepopt_dffmuxextEddie Hung2019-09-043-0/+60
| * Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
* | Merge pull request #1379 from mmicko/sim_modelsEddie Hung2019-09-182-7/+162
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| * | make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
| * | better lut handlingMiodrag Milanovic2019-09-181-4/+14
| * | better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
| * | Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-152-3/+141
* | | Add "write_aiger -L"Clifford Wolf2019-09-181-5/+16
* | | Fix stupid bug in btor back-endClifford Wolf2019-09-181-1/+1
* | | Bump versionClifford Wolf2019-09-161-1/+1
* | | Merge pull request #1380 from YosysHQ/clifford/fix1372Clifford Wolf2019-09-161-2/+9
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| * | | Fix handling of range selects on loop variables, fixes #1372Clifford Wolf2019-09-161-2/+9
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* | | Merge pull request #1374 from YosysHQ/eddie/fix1371Eddie Hung2019-09-152-5/+25
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| * | | SpacingEddie Hung2019-09-131-1/+1
| * | | Explicitly order function argumentsEddie Hung2019-09-131-4/+15
| * | | Use template specialisationEddie Hung2019-09-131-2/+9
| * | | Revert "SigSet<Cell*> to use stable compare class"Eddie Hung2019-09-135-6/+6
| * | | GrammarEddie Hung2019-09-121-1/+1
| * | | static_assert to enforce this going forwardEddie Hung2019-09-121-0/+2
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