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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-09-18 17:48:16 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-09-18 17:48:16 +0200 |
| commit | 3e9449cb0b7f3340c1a85983f40a5fb2e5e3f0da (patch) | |
| tree | de44803dc513ecfa8959323b226740b8c4877893 | |
| parent | b0ca6de472dcbba50776ac21cf450eb89ee33447 (diff) | |
| download | yosys-3e9449cb0b7f3340c1a85983f40a5fb2e5e3f0da.tar.gz yosys-3e9449cb0b7f3340c1a85983f40a5fb2e5e3f0da.tar.bz2 yosys-3e9449cb0b7f3340c1a85983f40a5fb2e5e3f0da.zip | |
make note that it is for latch mode
| -rw-r--r-- | techlibs/anlogic/cells_sim.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index cea9f8c11..0fba43572 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -55,6 +55,7 @@ module AL_MAP_SEQ ( end else begin + // DFFMODE == "LATCH" if (SRMODE == "ASYNC") begin always @(clk_ce, srmux) |