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* Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-192-17/+67
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* Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
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* Fix spacingEddie Hung2019-03-191-1/+1
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* shregmap -tech xilinx to delete $shiftx for var length SRLEddie Hung2019-03-191-10/+3
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* Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1953-38/+2398
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| * Merge pull request #885 from YosysHQ/clifford/fix873Clifford Wolf2019-03-191-2/+4
| |\ | | | | | | Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
| | * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #808 from eddiehung/read_aigerEddie Hung2019-03-1935-6/+632
| |\ | | | | | | Add new read_aiger frontend
| | * Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-19113-792/+6364
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| * | Merge pull request #884 from zachjs/masterClifford Wolf2019-03-192-1/+61
| |\ \ | | | | | | | | fix local name resolution in prefix constructs
| | * | fix local name resolution in prefix constructsZachary Snow2019-03-182-1/+61
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| * | Update issue templateClifford Wolf2019-03-171-5/+5
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Update issue templateClifford Wolf2019-03-171-0/+8
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #877 from FelixVi/masterClifford Wolf2019-03-161-1/+4
| |\ \ | | | | | | | | Add note about test requirements in README
| | * | Add note about test requirements in READMEFelix Vietmeyer2019-03-161-1/+4
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| * | Improve mix of src/wire/wirebit coverage in "mutate -list"Clifford Wolf2019-03-161-29/+84
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #876 from YosysHQ/clifford/fmcombineClifford Wolf2019-03-164-17/+374
| |\ \ | | | | | | | | Add fmcombine pass
| | * | Add "fmcombine -fwd -bwd -nop"Clifford Wolf2019-03-151-10/+59
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add fmcombine passClifford Wolf2019-03-154-17/+325
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #875 from YosysHQ/clifford/mutateClifford Wolf2019-03-154-5/+862
| |\ \ | | | | | | | | Add "mutate" pass
| | * | Improvements in "mutate" list-reduce algorithmClifford Wolf2019-03-151-13/+36
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate -cfg", improve pick_cover behaviorClifford Wolf2019-03-141-46/+101
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add a strictly coverage-driven mutation selection strategyClifford Wolf2019-03-141-1/+70
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Improve "mutate" wire coverage metricClifford Wolf2019-03-141-1/+16
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add more mutation types, improve mutation src coverClifford Wolf2019-03-141-92/+268
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Fix smtbmc.py handling of zero appended stepsClifford Wolf2019-03-141-5/+5
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate" command DB reduce functionalityClifford Wolf2019-03-141-12/+181
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add hashlib "<container>::element(int n)" methodsClifford Wolf2019-03-141-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add "mutate -mode inv", various other mutate improvementsClifford Wolf2019-03-141-99/+213
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add basic "mutate -list N" frameworkClifford Wolf2019-03-142-0/+230
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Disable realmath testsClifford Wolf2019-03-151-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #874 from YosysHQ/clifford/andoptClifford Wolf2019-03-141-0/+7
| |\ \ | | | | | | | | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
| | * | Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327Clifford Wolf2019-03-141-0/+7
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #872 from YosysHQ/clifford/pmuxfixClifford Wolf2019-03-142-1/+10
| |\ \ | | | | | | | | Improve handling of "full_case" attributes
| | * | Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Fix a syntax bug in ilang backend related to process case statementsClifford Wolf2019-03-141-1/+1
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #869 from cr1901/win-shellClifford Wolf2019-03-143-1/+377
| |\ \ | | | | | | | | Install launcher executable when running yosys-smtbmc on Windows.
| | * | Install launcher executable when running yosys-smtbmc on Windows.William D. Jones2019-03-133-1/+377
| | | | | | | | | | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
| | | * Add author nameEddie Hung2019-03-191-0/+1
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| | | * Add aiger tests to make testsEddie Hung2019-02-191-0/+1
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| | | * Merge branch 'master' into read_aigerEddie Hung2019-02-190-0/+0
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| | | * | Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
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| | | * | Missing OSX headers?Eddie Hung2019-02-171-0/+5
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| | | * | Revert "Missing headers for Xcode?"Eddie Hung2019-02-171-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit c23e3f07517d4818d9ab1b532250353492cf50c2.
| | | * | Merge branch 'dff_init' into read_aigerEddie Hung2019-02-173-104/+56
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| | | * | | read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
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| | | * | | One more merge conflictEddie Hung2019-02-171-6/+1
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| | | * | | Merge branch 'dff_init' into read_aigerEddie Hung2019-02-170-0/+0
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| | | * \ \ \ Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-179-100/+349
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