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| | | * | Improvements in "viz" commandClaire Xenia Wolf2022-12-071-17/+51
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| | | * Improvements in "viz" passClaire Xenia Wolf2022-12-071-313/+453
| | | * Various improvements in "viz" commandClaire Xenia Wolf2022-12-061-72/+242
| | | * Bugfix in splitcells passClaire Xenia Wolf2022-12-061-5/+13
| | | * Improvements in "viz" commandClaire Xenia Wolf2022-12-041-45/+196
| | | * Add "viz" pass for visualizing big-picture data flow in larger designsClaire Xenia Wolf2022-12-042-0/+511
| | | * Add splitcells passClaire Xenia Wolf2022-12-042-0/+192
| | | * Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuffClaire Xenia Wolf2022-12-042-1/+8
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* | | | Merge pull request #3567 from YosysHQ/tcl_fix_crashMiodrag Milanović2022-12-022-1/+8
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| * | | | Fix tcl crash in case of error executing commandMiodrag Milanovic2022-11-302-1/+8
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| | | * Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuffClaire Xenia Wolf2022-12-0129-79/+2537
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| | * | miter: Add -make_cover option to cover each output pair differenceJannis Harder2022-11-301-0/+14
| | * | formalff: Fix -ff2anyinit assertion error for fine FFsJannis Harder2022-11-301-0/+2
| | * | New xprop pass to encode 3-valued x-propagation using 2-valued logicJannis Harder2022-11-307-0/+2001
| | * | sim: Improved global clock handlingJannis Harder2022-11-301-13/+14
| | * | opt_expr: Optimizations for `$bweqx` and `$bwmux`Jannis Harder2022-11-301-0/+63
| | * | Add bwmuxmap passJannis Harder2022-11-307-0/+76
| | * | Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-309-11/+179
| | * | verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.Jannis Harder2022-11-301-2/+4
| | * | verilog_backend: Correctly sign extend output of signed `$modfloor`Jannis Harder2022-11-301-2/+2
| | * | verilog_backend: Add -noparallelcase optionJannis Harder2022-11-301-7/+31
| | * | simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signalJannis Harder2022-11-301-2/+8
| | * | simlib: Silence iverilog warning for `$lut`Jannis Harder2022-11-301-1/+1
| | * | simlib: Fix wide $bmux and avoid iverilog warningsJannis Harder2022-11-301-2/+2
| | * | satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-302-18/+20
| | * | opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
| | * | opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
| | * | opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
| | * | simplemap: Map `$xnor` to `$_XNOR_` cellsJannis Harder2022-11-293-20/+5
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| | * Add insbuf -chain modeClaire Xenia Wolf2022-12-011-2/+38
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* | Bump versiongithub-actions[bot]2022-12-011-1/+1
* | Merge pull request #3551 from daglem/struct-array-swapped-rangeJannis Harder2022-12-013-21/+192
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| * Added asserts for current limitation of array dimensions in packed structsDag Lem2022-11-301-0/+8
| * Check for all cases of currently unsupported array dimensions in packed structsDag Lem2022-11-301-10/+13
| * Tests for unpacked arrays in packed structs are for the Yosys frontend onlyDag Lem2022-11-231-0/+4
| * Support for swapped ranges in second array dimensionDag Lem2022-11-232-3/+52
| * Support for arrays with swapped ranges within structsDag Lem2022-11-123-11/+118
* | Bump versiongithub-actions[bot]2022-11-291-1/+1
* | Merge pull request #3565 from jix/sat-def-formalJannis Harder2022-11-283-10/+46
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| * | sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-283-10/+46
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* | Bump versiongithub-actions[bot]2022-11-261-1/+1
* | Merge pull request #3561 from YosysHQ/tcl_shellMiodrag Milanović2022-11-252-8/+34
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| * | Add TCL interactive shell modeMiodrag Milanovic2022-11-252-8/+34
* | | Merge pull request #3560 from YosysHQ/verific_confMiodrag Milanović2022-11-253-8/+43
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| * | update documentationMiodrag Milanovic2022-11-251-3/+3
| * | Support importing verilog configurations using VerificMiodrag Milanovic2022-11-253-5/+40
* | | Bump versiongithub-actions[bot]2022-11-251-1/+1
* | | Remove docs dependency on yosys repo (#3558)KrystalDelusion2022-11-2439-18/+905
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* | Merge pull request #3552 from daglem/fix-sv-c-array-dimensionsJannis Harder2022-11-231-3/+3
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| * | Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
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