| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 |
| * | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 |
| * | No need to punch ports at all | Eddie Hung | 2019-09-30 | 2 | -13/+24 |
| * | Resolve FIXME on calling proc just once | Eddie Hung | 2019-09-30 | 1 | -2/+2 |
| * | Cleanup $currQ from aigerparse | Eddie Hung | 2019-09-30 | 1 | -2/+0 |
| * | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 4 | -114/+129 |
| * | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
| * | Cleanup | Eddie Hung | 2019-09-30 | 1 | -100/+3 |
| * | Add comment | Eddie Hung | 2019-09-30 | 1 | -0/+1 |
| * | Use a cell_cache to instantiate once rather than opt_merge call | Eddie Hung | 2019-09-30 | 1 | -15/+15 |
| * | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 2 | -29/+28 |
| * | Use derived module | Eddie Hung | 2019-09-30 | 1 | -22/+5 |
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 29 | -132/+1981 |
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| | * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 |
| | * | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 11 | -0/+1767 |
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| | | * | rpc: new frontend. | whitequark | 2019-09-30 | 9 | -0/+744 |
| | | * | libs: import json11. | whitequark | 2019-09-30 | 3 | -0/+1023 |
| | * | | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors | Eddie Hung | 2019-09-30 | 1 | -0/+2 |
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| | | * | | Generate Python wrappers for inline constructors | Benedikt Tutzer | 2019-09-23 | 1 | -0/+2 |
| | * | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 4 | -6/+10 |
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| | | * | | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
| | | * | | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 4 | -5/+5 |
| | * | | | | Bump version | Clifford Wolf | 2019-09-30 | 1 | -1/+1 |
| | * | | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+2 |
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| | | * | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | Eddie Hung | 2019-09-27 | 1 | -0/+2 |
| | * | | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| | | * | | | | | Fix $dlatch handling in async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| | * | | | | | Add latch test modified from #1363 | Eddie Hung | 2019-09-30 | 2 | -0/+73 |
| | * | | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
| | * | | | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 3 | -2/+77 |
| * | | | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 45 | -281/+6242 |
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| | * | | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-map | Eddie Hung | 2019-09-29 | 1 | -0/+2 |
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| | | * | | | | | Avoid work in replace() if rules empty. | Henner Zeller | 2019-09-29 | 1 | -0/+2 |
| | * | | | | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 44 | -281/+6234 |
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| | | * | | | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
| | | * | | | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | | * | | | | | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | | * | | | | | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 |
| | | * | | | | | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 |
| | | * | | | | | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 |
| | | * | | | | | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 |
| | | * | | | | | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 |
| | | * | | | | | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 |
| | | * | | | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
| | | * | | | | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
| | | * | | | | | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 |
| | | * | | | | | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 |
| | | * | | | | | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |
| | | * | | | | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 |
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