| Commit message (Collapse) | Author | Age | Files | Lines |
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Unused outputs lead to undriven buffers, which lead to syntax errors.
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This uses the Trenz TEC0117 on Gowin IDE 1.8.4
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This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
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Fix #1496.
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write_verilog: add -extmem option, to write split memory init files
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Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Python Wrappers: Expose global variables and allow logging to python streams
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feature/python_wrappers/globals_and_streams
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(This is only relevant for classes that are exposed twice, one time as a
base class and one time as a derived class that can in turn be
overridden in python, but actually all others were renamed)
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Global variables are now accessible via the Yosys class.
To capture Yosys output, once can now register an output stream in
Pyosys.
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ice40: Support for post-place-and-route timing simulations
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: David Shah <dave@ds0.me>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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makaimann-label-bads-btor
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flowmap: fix a few crashes
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Fixes #1475.
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Fixes #1405.
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Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Add CodingReadme section on script passes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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write_verilog: do not print (*init*) attributes on regs
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If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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