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| * | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
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| * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
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| * | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
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| * | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
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| * | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
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| * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | Updating gowinDiego H2019-09-022-2/+2
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| * | | | | Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Unused outputs lead to undriven buffers, which lead to syntax errors.
| * | | | | Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| | | | | | | | | | | | | | | | | | | | | | | | This uses the Trenz TEC0117 on Gowin IDE 1.8.4
| * | | | | Merge branch 'master' of https://github.com/YosysHQ/yosysPepijn de Vos2019-09-043-5/+6
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| * | | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* | | | | | | Fix #1462, #1480.Marcin Kościelnicki2019-11-194-9/+40
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* | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* | | | | | | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fixClifford Wolf2019-11-182-4/+21
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Fix #1496.
| * | | | | | | Fix #1496.Marcin Kościelnicki2019-11-182-4/+21
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* | | | | | | | Merge pull request #1494 from whitequark/write_verilog-extmemwhitequark2019-11-181-10/+80
|\ \ \ \ \ \ \ \ | |/ / / / / / / |/| | | | | | | write_verilog: add -extmem option, to write split memory init files
| * | | | | | | write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
* | | | | | | | Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arstClifford Wolf2019-11-171-4/+10
|\ \ \ \ \ \ \ \ | |_|_|_|_|_|_|/ |/| | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUE
| * | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUEDavid Shah2019-11-141-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| |/ / / / / / |/| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-143-0/+136
|\ \ \ \ \ \ \ | |/ / / / / / |/| | | | | | Add "autoname" pass and use it in "synth_ice40"
| * | | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-133-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streamsClifford Wolf2019-11-141-6/+286
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | Python Wrappers: Expose global variables and allow logging to python streams
| * \ \ \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵Benedikt Tutzer2019-10-1525-61/+345
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | feature/python_wrappers/globals_and_streams
| * | | | | | | | Fix renaming all classes to Cpp*Benedikt Tutzer2019-10-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This is only relevant for classes that are exposed twice, one time as a base class and one time as a derived class that can in turn be overridden in python, but actually all others were renamed)
| * | | | | | | | Expose global variables and allow logging to python streamsBenedikt Tutzer2019-10-091-6/+286
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Global variables are now accessible via the Yosys class. To capture Yosys output, once can now register an output stream in Pyosys.
* | | | | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | ice40: Support for post-place-and-route timing simulations
| * | | | | | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | Merge branch 'makaimann-label-bads-btor'Clifford Wolf2019-11-141-1/+6
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| * | | | | | | | | | Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into ↵Clifford Wolf2019-11-141-1/+10
|/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | makaimann-label-bads-btor
| * | | | | | | | | | Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
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* | | | | | | | | | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
|\ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / |/| | | | | | | | | flowmap: fix a few crashes
| * | | | | | | | | flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1475.
| * | | | | | | | | flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1405.
* | | | | | | | | Merge pull request #1486 from YosysHQ/clifford/fsmdetectfixClifford Wolf2019-11-131-6/+10
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Bugfix in fsm_detect
| * | | | | | | | | Update fsm_detect bugfixClifford Wolf2019-11-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | Bugfix in fsm_detectClifford Wolf2019-11-121-6/+9
|/ / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge pull request #1484 from YosysHQ/clifford/cmp2luteqneClifford Wolf2019-11-126-18/+35
|\ \ \ \ \ \ \ \ \ | |/ / / / / / / / |/| | | | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
| * | | | | | | | Fixed testsMiodrag Milanovic2019-11-115-17/+34
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| * | | | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
|/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge pull request #1470 from YosysHQ/clifford/subpassdocClifford Wolf2019-11-101-0/+46
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Add CodingReadme section on script passes
| * | | | | | | | Add CodingReadme section on script passesClifford Wolf2019-10-311-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option.
* | | | | | | | | Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
|/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | write_verilog: do not print (*init*) attributes on regs
| * | | | | | | | write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.
* | | | | | | | | Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-24 02:09:58 +0000