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* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-162-4/+37
* json: Add support for memories.Marcelina Kościelnicka2021-03-152-0/+88
* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-152-23/+82
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-152-11/+24
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-152-18/+63
* Merge pull request #2658 from zachjs/parameters-across-fileswhitequark2021-03-143-1/+21
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| * sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-123-1/+21
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* Merge pull request #2653 from zachjs/global-parameterwhitequark2021-03-122-0/+18
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| * verilog: disallow overriding global parametersZachary Snow2021-03-112-0/+18
* | Merge pull request #2642 from whitequark/cxxrtl-noproc-fixeswhitequark2021-03-111-17/+29
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| * | cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| * | cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
* | | Add _pm.h files to GENLIST, fixes vcxsrc targetMiodrag Milanovic2021-03-111-0/+9
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* | Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
* | Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
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| * | Fix param without default log lineZachary Snow2021-03-071-1/+1
* | | Bump versionMarcelina Kościelnicka2021-03-081-1/+1
* | | memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-086-82/+19
* | | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-085-29/+94
* | | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-0816-43/+245
* | | sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
* | | proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-082-0/+27
* | | memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
* | | tests/bram: Do not generate write address collisions.Marcelina Kościelnicka2021-03-081-5/+23
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* | Replace assert in abc9_ops with more useful error messageDan Ravensloft2021-03-071-1/+9
* | Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0712-5/+225
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| * | sv: support for parameters without default valuesZachary Snow2021-03-0212-5/+225
* | | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-073-0/+39
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| * | | verilog: impose limit on maximum expression widthZachary Snow2021-03-043-0/+39
* | | | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-064-1/+70
* | | | proc_clean: Fix empty case removal conditions.Marcelina Kościelnicka2021-03-061-10/+21
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* | | Remove a few functions that, in fact, did not exist in the first place.Marcelina Kościelnicka2021-03-062-3/+1
* | | Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
* | | Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
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| * | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
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* | | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
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| * | | cxxrtl: add pass debug flag to show assigned wire types.whitequark2021-03-051-0/+46
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* | | Merge pull request #2633 from whitequark/cxxrtl-no-topwhitequark2021-03-051-1/+1
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| * | cxxrtl: don't crash on empty designs.whitequark2021-03-051-1/+1
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* | Update command-reference-manual.texClaire Xen2021-03-041-4/+4
* | Update READMEClaire Xen2021-03-041-4/+4
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* Merge pull request #2620 from zachjs/port-int-typeswhitequark2021-03-013-2/+64
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| * verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-013-2/+64
* | Bump versionMarcelina Kościelnicka2021-03-011-1/+1
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* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-018-11/+197
* Set aside extraneous tests in simple_abc9 test suiteZachary Snow2021-03-012-0/+19
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
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| * Fix indents.Tom Verbeure2021-01-041-2/+2
| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
* | Merge pull request #2524 from bkbncn/patch-1Claire Xen2021-03-011-0/+1
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