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| * | Merge pull request #933 from dh73/masterClifford Wolf2019-04-121-3/+9
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| | * | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | Merge pull request #932 from YosysHQ/eddie/fixdlatchClifford Wolf2019-04-122-3/+4
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| | * Add default entry to testcaseEddie Hung2019-04-111-2/+3
| | * Recognise default entry in case even if all cases covered (#931)Eddie Hung2019-04-111-1/+1
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| * Fix a few typosEddie Hung2019-04-081-3/+3
* | Add non-input bits driven by unrecognised cells as ci_bitsEddie Hung2019-04-101-1/+1
* | parse_aiger() to rename all $lut cells after "clean"Eddie Hung2019-04-101-24/+21
* | More space fixingEddie Hung2019-04-081-2/+2
* | Fix spacingEddie Hung2019-04-081-29/+29
* | Merge branch 'master' into xaigEddie Hung2019-04-08115-710/+5842
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| * Merge pull request #919 from YosysHQ/multiport_transpClifford Wolf2019-04-081-1/+2
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| | * memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
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| * Add "read_ilang -lib"Clifford Wolf2019-04-055-3/+39
| * Added missing argument checking to "mutate" commandClifford Wolf2019-04-041-0/+32
| * Merge pull request #913 from smunaut/fix_proc_muxEddie Hung2019-04-031-1/+1
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| | * proc_mux: Fix crash when trying to optimize non-existant mux to shiftxSylvain Munaut2019-04-031-1/+1
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| * Merge pull request #912 from YosysHQ/bram_addr_enClifford Wolf2019-04-031-0/+2
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| | * memory_bram: Consider read enable for address expansion registerDavid Shah2019-04-021-0/+2
| * | Merge pull request #910 from ucb-bar/memupdatesClifford Wolf2019-04-031-30/+173
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| | * Refine memory support to deal with general Verilog memory definitions.Jim Lawson2019-04-011-30/+173
| * | Merge pull request #895 from YosysHQ/pmux2shiftxEddie Hung2019-04-021-0/+28
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| | * Create one $shiftx per bit in widthEddie Hung2019-03-251-10/+17
| | * Add a pmux-to-shiftx optimisation to proc_muxEddie Hung2019-03-231-0/+21
| * | Merge pull request #907 from YosysHQ/clifford/fix906Clifford Wolf2019-03-301-0/+2
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| | * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
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| * | Merge pull request #901 from trcwm/libertyfixesClifford Wolf2019-03-284-9/+151
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| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
| | * | Liberty file parser now accepts superfluous ;Niels Moseley2019-03-274-9/+151
| * | | Merge pull request #903 from YosysHQ/bram_reset_transpClifford Wolf2019-03-281-0/+1
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| | * | memory_bram: Reset make_transp when growing read portsDavid Shah2019-03-271-0/+1
| * | | Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
| * | | Add "rename -output"Clifford Wolf2019-03-271-3/+23
| * | | Improve "rename" help messageClifford Wolf2019-03-271-0/+6
| * | | Add "cutpoint -undef"Clifford Wolf2019-03-261-10/+14
| * | | Add "hdlname" attributeClifford Wolf2019-03-262-0/+5
| * | | Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-262-15/+93
| * | | Add "cutpoint" passClifford Wolf2019-03-252-0/+165
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| * | Merge pull request #896 from YosysHQ/transp_fixesClifford Wolf2019-03-251-9/+16
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| | * | memory_bram: Fix multiclock make_transpDavid Shah2019-03-241-9/+16
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| * | Merge pull request #897 from trcwm/libertyfixesClifford Wolf2019-03-258-22/+645
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| | * spaces -> tabsNiels Moseley2019-03-251-78/+78
| | * EOL is now accepted as ';' replacement on lines that look like: feature_xyz(o...Niels Moseley2019-03-251-4/+3
| | * Updated the liberty parser to accept [A:B] ranges (AST has not been updated)....Niels Moseley2019-03-248-7/+631
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| * Add "mutate -none -mode", "mutate -mode none"Clifford Wolf2019-03-231-1/+30
| * Add "mutate -s <filename>"Clifford Wolf2019-03-231-2/+24
| * Merge pull request #893 from YosysHQ/clifford/btormeminitClifford Wolf2019-03-233-3/+63
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| | * Add support for memory initialization to write_btorClifford Wolf2019-03-231-0/+53
| | * Fix BTOR output tags syntax in writye_btorClifford Wolf2019-03-231-2/+1
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