| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Be more explicit | Eddie Hung | 2019-07-19 | 1 | -6/+29 |
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| * | wreduce for $sub | Eddie Hung | 2019-07-19 | 1 | -0/+23 |
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| * | Add tests for sub too | Eddie Hung | 2019-07-19 | 1 | -1/+48 |
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| * | Add test | Eddie Hung | 2019-07-19 | 1 | -0/+22 |
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| * | SigSpec::extract to take negative lengths | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| * | Merge pull request #1208 from ZirconiumX/intel_cleanups | David Shah | 2019-07-18 | 1 | -29/+14 |
| |\ | | | | | Assorted synth_intel cleanups from @bwidawsk | ||||
| | * | synth_intel: Use stringf | Dan Ravensloft | 2019-07-18 | 1 | -7/+2 |
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| | * | synth_intel: s/not family/no family/ | Dan Ravensloft | 2019-07-18 | 1 | -2/+2 |
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| | * | synth_intel: revert change to run_max10 | Dan Ravensloft | 2019-07-18 | 1 | -1/+1 |
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| | * | intel_synth: Fix help message | Ben Widawsky | 2019-07-18 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | intel_synth: Small code cleanup to remove if ladder | Ben Widawsky | 2019-07-18 | 2 | -29/+11 |
| | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | intel_synth: Make family explicit and match | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | intel_synth: Minor code cleanups | Ben Widawsky | 2019-07-18 | 1 | -2/+6 |
| | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | Merge pull request #1207 from ZirconiumX/intel_new_pass_names | David Shah | 2019-07-18 | 1 | -4/+4 |
| |\ \ | |/ |/| | synth_intel: rename for consistency with #1184 | ||||
| | * | synth_intel: rename for consistency with #1184 | Dan Ravensloft | 2019-07-18 | 1 | -4/+4 |
| |/ | | | | Also fix a typo in the help message. | ||||
| * | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 5 | -17/+21 |
| |\ | | | | | synth_{ice40,ecp5}: more sensible pass label naming | ||||
| | * | synth_ecp5: rename dram to lutram everywhere. | whitequark | 2019-07-16 | 4 | -13/+13 |
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| | * | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 2 | -5/+9 |
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| * | | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 |
| |\ \ | | | | | | | write_verilog: dump zero width constants correctly | ||||
| | * | | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again). | ||||
| * | | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #1204 from smunaut/fix_1187 | David Shah | 2019-07-17 | 2 | -4/+4 |
| |\ \ \ | |/ / |/| | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map | ||||
| | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | | Merge pull request #1202 from YosysHQ/cmp2lut_lut6 | Eddie Hung | 2019-07-16 | 4 | -24/+37 |
| |\ \ \ | |/ / |/| | | cmp2lut transformation to support >32 bit LUT masks | ||||
| | * | | gen_lut to return correctly sized LUT mask | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
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| | * | | Forgot to commit | Eddie Hung | 2019-07-16 | 1 | -0/+7 |
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| | * | | Add tests for cmp2lut on LUT6 | Eddie Hung | 2019-07-16 | 2 | -23/+29 |
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| * | | Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters | Eddie Hung | 2019-07-16 | 2 | -45/+128 |
| |\ \ | | | | | | | abc9: push inverters driving box inputs (comb outputs) through $lut soft logic | ||||
| | * | | Add comment | Eddie Hung | 2019-07-13 | 1 | -0/+5 |
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| | * | | Update test with more accurate LUT mask | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | | duplicate -> clone | Eddie Hung | 2019-07-12 | 1 | -3/+3 |
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| | * | | More cleanup | Eddie Hung | 2019-07-12 | 1 | -8/+2 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -29/+51 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -10/+4 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -15/+24 |
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| | * | | More cleanup | Eddie Hung | 2019-07-12 | 1 | -11/+10 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -46/+16 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -7/+1 |
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| | * | | Cleanup | Eddie Hung | 2019-07-12 | 1 | -13/+109 |
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| * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 9 | -31/+122 |
| |\ \ | | | | | | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | ||||
| | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 |
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| | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 |
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| | * | | Do not double count cells in abc | Eddie Hung | 2019-07-12 | 1 | -2/+2 |
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| | * | | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | | Remove double push | Eddie Hung | 2019-07-12 | 1 | -1/+0 |
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| | * | | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 |
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| | * | | ice40_opt to handle this box and opt back to SB_LUT4 | Eddie Hung | 2019-07-12 | 1 | -0/+48 |
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| | * | | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 |
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index : iCE40/yosys | |
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