diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 19:21:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-12 19:30:18 -0700 |
| commit | be0cb7f4b81af91ce47a8baf57d0aff716eecddc (patch) | |
| tree | d7236f44625c4877cb5a961d57e8737837c00567 | |
| parent | 7d583f9e57dc3feb7e525c5ad120b1ba3959fdcd (diff) | |
| download | yosys-be0cb7f4b81af91ce47a8baf57d0aff716eecddc.tar.gz yosys-be0cb7f4b81af91ce47a8baf57d0aff716eecddc.tar.bz2 yosys-be0cb7f4b81af91ce47a8baf57d0aff716eecddc.zip | |
More cleanup
| -rw-r--r-- | passes/techmap/abc9.cc | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7b1c9f815..36f2fafc3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -30,8 +30,7 @@ "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\ "&mfs; &ps -l" #else -#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs -b; &ps -l" -//#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &put -v; dch -f; if {W} {D} -vo; mfs2; &get -vm; &ps -l" +#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l" #endif @@ -756,16 +755,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit a_bit = not_cell->getPort("\\A"); RTLIL::SigBit y_bit = not_cell->getPort("\\Y"); RTLIL::Const driver_mask; - RTLIL::Wire *orig_a_bit_wire = a_bit.wire; - decltype(bit2sinks)::const_iterator jt; a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name)); y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name)); - if (orig_a_bit_wire->port_output) - goto duplicate_lut; - - jt = bit2sinks.find(a_bit); + auto jt = bit2sinks.find(a_bit); if (jt == bit2sinks.end()) goto duplicate_lut; |