| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | | manual: document behavior of many comb cells more precisely. | whitequark | 2019-12-04 | 1 | -35/+56 | |
| * | | | | | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 2 | -9/+16 | |
| * | | | | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 2 | -146/+196 | |
| * | | | | | xilinx: Add models for LUTRAM cells. (#1537) | Marcin Kościelnicki | 2019-12-04 | 3 | -624/+831 | |
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| * | | | | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 5 | -114/+571 | |
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| | * | | | | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 | |
| | * | | | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 2 | -11/+13 | |
| | * | | | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 2 | -292/+292 | |
| | * | | | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 4 | -41/+495 | |
| * | | | | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix | David Shah | 2019-12-02 | 2 | -29/+46 | |
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| | * | | | | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 2 | -29/+46 | |
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| * | | | | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check | Clifford Wolf | 2019-12-01 | 1 | -0/+4 | |
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| | * | | | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 | |
| * | | | | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll | Miodrag Milanović | 2019-11-29 | 2 | -0/+21 | |
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| | * | | | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| * | | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
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| * | | | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 2 | -3/+72 | |
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| | * | | | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 | |
| | * | | | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 | |
| | * | | | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 | |
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| * | | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 | |
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| | * | | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| * | | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 | |
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| | * | | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 2 | -4/+24 | |
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| * | | | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve | Eddie Hung | 2019-11-27 | 2 | -22/+5 | |
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| | * | | | | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
| | * | | | | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 | |
| | * | | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| * | | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
| * | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 4 | -6/+69 | |
| * | | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 5 | -10/+14 | |
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| * | | | Merge pull request #1520 from pietrmar/fix-1463 | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
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| | * | | | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 | |
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| * | | | Merge pull request #1517 from YosysHQ/clifford/optmem | Clifford Wolf | 2019-11-22 | 3 | -0/+146 | |
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| | * | | | Add "opt_mem" pass | Clifford Wolf | 2019-11-22 | 3 | -0/+146 | |
| * | | | | Merge pull request #1515 from YosysHQ/clifford/svastuff | Clifford Wolf | 2019-11-22 | 2 | -7/+39 | |
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| | * | | | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 | |
| | * | | | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 | |
| | * | | | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 | |
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| * | | | Merge pull request #1511 from YosysHQ/dave/always | Clifford Wolf | 2019-11-22 | 6 | -9/+126 | |
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| | * | | | Update CHANGELOG and README | David Shah | 2019-11-22 | 2 | -0/+7 | |
| | * | | | sv: Add tests for SV always types | David Shah | 2019-11-21 | 1 | -0/+63 | |
| | * | | | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage | David Shah | 2019-11-21 | 1 | -4/+16 | |
| | * | | | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 | |
| * | | | | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 | |
| * | | | | gowin: Add missing .gitignore entries | Marcin Kościelnicki | 2019-11-22 | 1 | -0/+2 | |
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| * | | | Merge pull request #1507 from YosysHQ/clifford/verificfixes | Clifford Wolf | 2019-11-20 | 2 | -6/+9 | |
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