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* abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
* Fix commentEddie Hung2019-12-091-1/+1
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-0619-971/+1773
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| * Merge pull request #1555 from antmicro/fix-macc-xilinx-testEddie Hung2019-12-061-1/+1
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| | * tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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| * Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-053-43/+82
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| | * kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-042-8/+26
| | * manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
| * | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| * | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
| * | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
| * | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
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| | * | update testPepijn de Vos2019-12-031-2/+3
| | * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-032-11/+13
| | * | attempt to fix formattingPepijn de Vos2019-11-252-292/+292
| | * | gowin: add and test dff init valuesPepijn de Vos2019-11-254-41/+495
| * | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fixDavid Shah2019-12-022-29/+46
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| | * | | abc9: Fix breaking of SCCsDavid Shah2019-12-012-29/+46
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| * | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-checkClifford Wolf2019-12-011-0/+4
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| | * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
| * | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpllMiodrag Milanović2019-11-292-0/+21
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| | * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
| * | | | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
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* | | | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-062-94/+87
* | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
* | | | Do not connect undriven POs to 1'bxEddie Hung2019-12-061-8/+3
* | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type asEddie Hung2019-12-061-39/+15
* | | | Fix writing non-whole modules, including inouts and keepsEddie Hung2019-12-061-90/+81
* | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
* | | | write_xaiger to support part-selected modules againEddie Hung2019-12-051-11/+37
* | | | abc9 to do clock partitioning againEddie Hung2019-12-051-37/+144
* | | | Remove clkpartEddie Hung2019-12-053-313/+0
* | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
* | | | Missing wire declarationEddie Hung2019-12-041-0/+1
* | | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-042-118/+292
* | | | Oh deary meEddie Hung2019-12-041-4/+4
* | | | Bump ABC to get "&verify -s" fixEddie Hung2019-12-041-1/+1
* | | | output reg Q -> output Q to suppress warningEddie Hung2019-12-041-8/+8
* | | | abc9_map.v to do `zinit' and make INIT = 1'b0Eddie Hung2019-12-041-70/+112
* | | | CleanupEddie Hung2019-12-031-11/+12
* | | | Add assertionEddie Hung2019-12-031-0/+1
* | | | write_xaiger to consume abc9_init attribute for abc9_flopsEddie Hung2019-12-031-34/+28
* | | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-032-4/+24
* | | | Revert "Add INIT value to abc9_control"Eddie Hung2019-12-031-8/+8
* | | | Update ABCREV for upstream bugfixEddie Hung2019-12-031-1/+1
* | | | techmap abc_unmap.v before xilinx_srl -fixedEddie Hung2019-12-031-6/+5
* | | | Add INIT value to abc9_controlEddie Hung2019-12-021-8/+8
* | | | CleanupEddie Hung2019-12-011-3/+2
* | | | Use pool instead of std::set for determinismEddie Hung2019-12-011-1/+1
* | | | Use pool<> not std::set<> for determinismEddie Hung2019-12-011-4/+4
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