| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | | | | | | Merge pull request #2095 from rswarbrick/hier-typo | whitequark | 2020-05-28 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | Fix small typos in documentation for hierarchy command | Rupert Swarbrick | 2020-05-28 | 1 | -2/+2 | |
| * | | | | | | | | | | | | Merge pull request #2091 from boqwxp/printattrs | whitequark | 2020-05-28 | 3 | -0/+105 | |
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| | * | | | | | | | | | | | printattrs: Simplify `get_indent_str()`. | Alberto Gonzalez | 2020-05-28 | 1 | -3/+1 | |
| | * | | | | | | | | | | | printattrs: Refactor indentation string building for clarity. | Alberto Gonzalez | 2020-05-27 | 1 | -5/+11 | |
| | * | | | | | | | | | | | printattrs: Add test. | Alberto Gonzalez | 2020-05-27 | 1 | -0/+14 | |
| | * | | | | | | | | | | | printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately. | Alberto Gonzalez | 2020-05-27 | 1 | -8/+15 | |
| | * | | | | | | | | | | | misc: Add `printattrs` command. | Alberto Gonzalez | 2020-05-27 | 2 | -0/+80 | |
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| * | | | | | | | | | | | Merge pull request #2051 from Xiretza/makefile-cd-warning | whitequark | 2020-05-28 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | Suppress warning during initial clone of ABC repo | Xiretza | 2020-05-14 | 1 | -1/+1 | |
| * | | | | | | | | | | | | Merge pull request #2031 from epfl-vlsc/master | whitequark | 2020-05-28 | 1 | -1/+40 | |
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| | * | | | | | | | | | | | | Formatting fixes | Sahand Kashani | 2020-05-06 | 1 | -14/+7 | |
| | * | | | | | | | | | | | | Add extmodule support to firrtl backend | Sahand Kashani | 2020-05-06 | 1 | -1/+47 | |
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| * | | | | | | | | | | | | Merge pull request #2063 from boqwxp/techmapped-firrtl | whitequark | 2020-05-28 | 1 | -10/+12 | |
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| | * | | | | | | | | | | | | firrtl: Accept techmapped cell types in FIRRTL backend. | Alberto Gonzalez | 2020-05-17 | 1 | -10/+12 | |
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| * | | | | | | | | | | | | Merge pull request #2088 from rswarbrick/count-at | whitequark | 2020-05-28 | 1 | -2/+8 | |
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| | * | | | | | | | | | | | | Minor optimisation in Module::wire() and Module::cell() | Rupert Swarbrick | 2020-05-26 | 1 | -2/+8 | |
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| * | | | | | | | | | | | | Merge pull request #2087 from rswarbrick/lex-warn | whitequark | 2020-05-28 | 1 | -1/+3 | |
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| | * | | | | | | | | | | | | Silence spurious warning in Verilog lexer when compiling with GCC | Rupert Swarbrick | 2020-05-26 | 1 | -1/+3 | |
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| * | | | | | | | | | | | | Merge pull request #2086 from rswarbrick/sigbit | whitequark | 2020-05-28 | 1 | -2/+1 | |
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| | * | | | | | | | | | | | | Use default copy constructor for RTLIL::SigBit | Rupert Swarbrick | 2020-05-26 | 1 | -2/+1 | |
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| * | | | | | | | | | | | | Merge pull request #2084 from rswarbrick/c_str | whitequark | 2020-05-28 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | Use c_str(), not str() for IdString/std::string == and != operators | Rupert Swarbrick | 2020-05-26 | 1 | -2/+2 | |
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| * | | | | | | | | | | | Merge pull request #2090 from whitequark/cxxrtl-fixes | whitequark | 2020-05-26 | 1 | -7/+13 | |
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| | * | | | | | | | | | | cxxrtl: make logging a little bit nicer. | whitequark | 2020-05-26 | 1 | -2/+10 | |
| | * | | | | | | | | | | cxxrtl: add missing parts of commit 281c9685. | whitequark | 2020-05-26 | 1 | -5/+3 | |
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| * | | | | | | | | | | Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy | Eddie Hung | 2020-05-25 | 3 | -13/+15 | |
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| | * | | | | | | | | | tests: xilinx macc test to have initval, shorten BMC depth for runtime | Eddie Hung | 2020-05-25 | 2 | -8/+8 | |
| | * | | | | | | | | | xilinx: tidy up cells_sim.v a little | Eddie Hung | 2020-05-25 | 1 | -5/+7 | |
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| * | | | | | | | | | Merge pull request #2044 from YosysHQ/eddie/fix2037 | Eddie Hung | 2020-05-25 | 2 | -20/+85 | |
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| | * | | | | | | | | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 | |
| | * | | | | | | | | test: add attribute-before-stmt test from @nakengelhardt | Eddie Hung | 2020-05-25 | 1 | -0/+15 | |
| | * | | | | | | | | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 2 | -6/+4 | |
| | * | | | | | | | | tests: add an generate-else test too | Eddie Hung | 2020-05-25 | 1 | -0/+34 | |
| | * | | | | | | | | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 | |
| | * | | | | | | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 | |
| | * | | | | | | | | tests: add #2037 testcase | Eddie Hung | 2020-05-25 | 1 | -0/+9 | |
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| * | | | | | | | | Merge pull request #2015 from boqwxp/qbfsat-bisection | clairexen | 2020-05-25 | 1 | -98/+207 | |
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| | * | | | | | | | | qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d60f9ad4c... | Alberto Gonzalez | 2020-05-23 | 1 | -11/+0 | |
| | * | | | | | | | | qbfsat: Add bisection mode and make it the default. | Alberto Gonzalez | 2020-05-23 | 1 | -87/+207 | |
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| * | | | | | | | | Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2020-05-24 | 2 | -7/+14 | |
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| | * | | | | | | | | xaiger: add testcase | Eddie Hung | 2020-05-24 | 1 | -0/+13 | |
| | * | | | | | | | | xaiger: do not derive cells | Eddie Hung | 2020-05-24 | 1 | -7/+1 | |
| * | | | | | | | | | Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup | Eddie Hung | 2020-05-23 | 3 | -14/+0 | |
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| | * | | | | | | | | ecp5: cleanup unused +/ecp5/abc9_model.v | Eddie Hung | 2020-05-23 | 3 | -14/+0 | |
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| * | | | | | | | | Merge pull request #2072 from whitequark/cxxrtl-dont-purge | whitequark | 2020-05-22 | 1 | -8/+2 | |
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| | * | | | | | | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level. | whitequark | 2020-05-22 | 1 | -8/+2 | |
| * | | | | | | | | | abc9_ops: update comment | Eddie Hung | 2020-05-21 | 1 | -1/+1 | |
| * | | | | | | | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 2 | -11/+37 | |
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| | * | | | | | | | | | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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