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authorEddie Hung <eddie@fpgeh.com>2020-05-24 08:48:23 -0700
committerEddie Hung <eddie@fpgeh.com>2020-05-24 08:48:23 -0700
commit33b03ce904f6810437e27ca7a6df4fb1e966fc23 (patch)
treef0e5b382ed2ff318ca6d964c29293eac7c8575c0
parentd64df216302bab5b7c5047bbbcb0e3cd82f1ec2d (diff)
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xaiger: add testcase
-rw-r--r--tests/various/xaiger.ys13
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys
new file mode 100644
index 000000000..f612d2e18
--- /dev/null
+++ b/tests/various/xaiger.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null