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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-21 11:00:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-21 11:00:36 -0700 |
| commit | 574812d9a54881784b104c71ba56a2e6ed14d39f (patch) | |
| tree | a0c659648a7a541602d9b68db5910c9586d5c7fb | |
| parent | 637650597b27a2e2f5407fc128ffd21d7a0b3016 (diff) | |
| parent | 38e858af8d5f61677d9686c022c864857f729d58 (diff) | |
| download | yosys-574812d9a54881784b104c71ba56a2e6ed14d39f.tar.gz yosys-574812d9a54881784b104c71ba56a2e6ed14d39f.tar.bz2 yosys-574812d9a54881784b104c71ba56a2e6ed14d39f.zip | |
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 20 | ||||
| -rw-r--r-- | tests/verilog/task_attr.ys | 28 |
2 files changed, 37 insertions, 11 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f250d7685..d39b72547 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2228,24 +2228,24 @@ simple_behavioral_stmt: behavioral_stmt: defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | - simple_behavioral_stmt ';' | ';' | - hierarchical_id attr { + attr simple_behavioral_stmt ';' | ';' | + attr hierarchical_id { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | - TOK_MSG_TASKS attr { + attr TOK_MSG_TASKS { AstNode *node = new AstNode(AST_TCALL); - node->str = *$1; - delete $1; + node->str = *$2; + delete $2; ast_stack.back()->children.push_back(node); ast_stack.push_back(node); - append_attr(node, $2); + append_attr(node, $1); } opt_arg_list ';'{ ast_stack.pop_back(); } | @@ -2342,8 +2342,6 @@ behavioral_stmt: ast_stack.pop_back(); }; - ; - unique_case_attr: /* empty */ { $$ = false; diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys new file mode 100644 index 000000000..d6e75f85f --- /dev/null +++ b/tests/verilog/task_attr.ys @@ -0,0 +1,28 @@ +read_verilog <<EOT +module top; + task foo; + endtask + + always @* + (* foo *) foo; + + initial + if (0) $info("bar"); +endmodule +EOT +# Since task enables are not an RTLIL object, +# any attributes on their AST get dropped +select -assert-none a:* a:src %d + + +logger -expect error "syntax error, unexpected ATTR_BEGIN" 1 +design -reset +read_verilog <<EOT +module top; + task foo; + endtask + + always @* + foo (* foo *); +endmodule +EOT |