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* machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires ↵William D. Jones2021-02-232-1/+17
| | | | to IO cells.
* machxo2: Add missing OSCH oscillator primitive.William D. Jones2021-02-231-0/+10
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* machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
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* machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
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* machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
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* machxo2: Add -noiopad option to synth_machxo2.William D. Jones2021-02-231-2/+11
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* machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.William D. Jones2021-02-231-1/+1
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* machxo2: Fix cells_sim typo where OFX1 was multiply-driven.William D. Jones2021-02-231-1/+1
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* machxo2: synth_machxo2 now maps ports to FACADE_IO.William D. Jones2021-02-232-0/+12
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* machxo2: Add initial value for Q in FACADE_FF.William D. Jones2021-02-231-0/+2
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* machxo2: Add FACADE_IO simulation model. More comments on models.William D. Jones2021-02-231-0/+25
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* machxo2: Add FACADE_SLICE simulation model.William D. Jones2021-02-231-0/+83
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* machxo2: Improve FACADE_FF simulation model.William D. Jones2021-02-231-12/+20
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* machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.William D. Jones2021-02-232-4/+4
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* machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
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* machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-232-1/+11
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* machxo2: Fix more oversights in machxo2 models. logic.ys test passes.William D. Jones2021-02-232-2/+6
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* machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-234-0/+15
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* machxo2: Fix typos. test/arch/run-test.sh passes.William D. Jones2021-02-232-2/+2
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* machxo2: Create basic techlibs and synth_machxo2 pass.William D. Jones2021-02-234-0/+320
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* frontend: json: parse negative valuesKarol Gugala2021-02-231-2/+10
| | | | Signed-off-by: Karol Gugala <kgugala@antmicro.com>
* assertpmux: Fix crash on unused $pmux output.Marcelina Kościelnicka2021-02-222-1/+19
| | | | Fixes #2595.
* Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-215-19/+195
|\ | | | | verilog: support recursive functions using ternary expressions
| * verilog: support recursive functions using ternary expressionsZachary Snow2021-02-125-19/+195
| | | | | | | | | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* | Merge pull request #2591 from zachjs/verilog-preproc-unappliedwhitequark2021-02-213-1/+32
|\ \ | | | | | | verilog: error on macro invocations with missing argument lists
| * | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-193-1/+32
|/ / | | | | | | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* | Bump versionYosys Bot2021-02-181-1/+1
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* | Merge pull request #2590 from RobertBaruch/fix_fast_sop_modeClaire Xen2021-02-171-1/+1
|\ \ | | | | | | Fixes command line for abc pass in -fast -sop mode
| * | Fixes command line for abc pass in -fast -sop modeRobert Baruch2021-02-161-1/+1
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* | Bump versionYosys Bot2021-02-161-1/+1
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* | Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
|\ \ | | | | | | Accept disable case for SVA liveness properties.
| * | Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
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* | | Bump versionYosys Bot2021-02-131-1/+1
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* | Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
|\ \ | | | | | | nexus: Add MULTADDSUB9X9WIDE sim model
| * | nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
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* | | Bump versionYosys Bot2021-02-121-1/+1
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* | | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-114-72/+176
|\ \ \ | | | | | | | | verilog: refactored constant function evaluation
| * | | verilog: refactored constant function evaluationZachary Snow2021-02-044-72/+176
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-113-4/+29
|\ \ \ | | | | | | | | verlog: allow shadowing module ports within generate blocks
| * | | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-073-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | | Merge pull request #2584 from antmicro/atom_type_signednessZachary Snow2021-02-112-4/+23
|\ \ \ \ | |/ / / |/| | | verilog_parser: fix missing is_signed attribute in type_atom
| * | | Add missing is_signed to type_atomKamil Rakoczy2021-02-112-4/+23
|/ / / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | Bump versionYosys Bot2021-02-071-1/+1
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* | | Merge pull request #2576 from zachjs/port-bind-sign-uniopwhitequark2021-02-063-8/+33
|\ \ \ | | | | | | | | genrtlil: fix signed port connection codegen failures
| * | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-053-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | | | Bump versionYosys Bot2021-02-061-1/+1
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* | | Merge pull request #2572 from antmicro/check-labelswhitequark2021-02-052-0/+28
|\ \ \ | | | | | | | | verilog_parser: add label check to gen_block
| * | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-042-0/+28
| |/ / | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* / / Bump versionYosys Bot2021-02-051-1/+1
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