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| author | William D. Jones <thor0505@comcast.net> | 2020-11-26 22:34:46 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | c31b17a2e28ac5f70600ee8b27f0befb3a1706be (patch) | |
| tree | 95038075452c4303c09a19c61e085828bc40cedf | |
| parent | c7aaa88f5807c7d49346b43b830a9826c52061ee (diff) | |
| download | yosys-c31b17a2e28ac5f70600ee8b27f0befb3a1706be.tar.gz yosys-c31b17a2e28ac5f70600ee8b27f0befb3a1706be.tar.bz2 yosys-c31b17a2e28ac5f70600ee8b27f0befb3a1706be.zip | |
machxo2: Add believed-to-be-correct tribuf test.
| -rw-r--r-- | tests/arch/machxo2/tribuf.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys new file mode 100644 index 000000000..7f3cd326e --- /dev/null +++ b/tests/arch/machxo2/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 3 t:FACADE_IO +select -assert-none t:FACADE_IO %% t:* %D |