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* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-092-2/+27
* Added back-end auto-detect for .edif and .jsonClifford Wolf2015-04-091-0/+4
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-092-7/+12
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
* Fixed const2big performance bugClifford Wolf2015-04-091-14/+21
* techmap code cleanupClifford Wolf2015-04-091-10/+6
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
* Added support for "file names with blanks"Clifford Wolf2015-04-087-33/+43
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-082-10/+1
* Added %M and %C select operatorsClifford Wolf2015-04-071-1/+38
* Added "pmuxtree" commandClifford Wolf2015-04-073-0/+164
* Added "chparam -list"Clifford Wolf2015-04-071-0/+21
* Added decoder generation to "muxcover"Clifford Wolf2015-04-071-13/+104
* Added hashlib support for std::tuple<>Clifford Wolf2015-04-071-0/+15
* Added "muxcover" commandClifford Wolf2015-04-072-0/+542
* Added pool<K>::pop()Clifford Wolf2015-04-071-0/+8
* typo fixClifford Wolf2015-04-071-1/+1
* Added "chparam" commandClifford Wolf2015-04-071-0/+57
* Added support for initialized xilinx bramsClifford Wolf2015-04-0611-92/+315
* Added support for initialized bramsClifford Wolf2015-04-062-9/+45
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
* Added "port_directions" to write_json outputClifford Wolf2015-04-061-0/+20
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-053-11/+16
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-051-6/+6
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-054-2/+131
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-046-8/+132
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* appnote 012 fixClifford Wolf2015-04-041-2/+2
* Appnote 012Clifford Wolf2015-04-042-115/+115
* Updated ABC to 51705b168d7aClifford Wolf2015-04-041-2/+2
* Merge pull request #55 from ahmedirfan1983/masterClifford Wolf2015-04-044-27/+492
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| * Update READMEAhmed Irfan2015-04-031-1/+1
| * Delete btor.ysAhmed Irfan2015-04-031-18/+0
| * Update READMEAhmed Irfan2015-04-031-1/+1
| * separated memory next from write cellAhmed Irfan2015-04-031-7/+55
| * Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2015-04-03266-4671/+18443
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* | documentation improvementsClifford Wolf2015-03-292-1/+5
* | Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* | Fixes in cmos_cells.vClifford Wolf2015-03-251-3/+12
* | Fixed detection of absolute paths in ABC for win32Clifford Wolf2015-03-223-3/+13
* | Added blif reference to appnote 010Clifford Wolf2015-03-221-1/+5
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-03-201-2/+2
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| * | Fixed handling of quotes in liberty parserClifford Wolf2015-03-181-2/+2
* | | fix for python 2.6.6Clifford Wolf2015-03-203-165/+172
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* | Added hierarchy -auto-topClifford Wolf2015-03-181-1/+33
* | Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* | Documentation for JSON format, added attributesClifford Wolf2015-03-061-16/+156
* | Added very first version of "synth_ice40"Clifford Wolf2015-03-054-0/+211
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