iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #740 from daveshah1/improve_dress	Clifford Wolf	2019-02-22	3	-34/+65
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\| *	ecp5: Use abc -dress	David Shah	2019-02-06	1	-2/+2
\| *	abc: Improved recovered netnames, also preserve src on nets with dress	David Shah	2019-02-06	1	-4/+13
\| *	ice40: Use abc -dress in synth_ice40	David Shah	2019-02-06	1	-1/+1
\| *	abc: Preserve naming through ABC using 'dress' command	David Shah	2019-02-06	1	-29/+51
* \|	Hotfix for 4c82ddf	Clifford Wolf	2019-02-21	1	-11/+2
* \|	Merge pull request #822 from litghost/expand_setundef	Clifford Wolf	2019-02-21	1	-0/+29
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\| * \|	Add -params mode to force undef parameters in selected cells.	Keith Rothman	2019-02-21	1	-0/+29
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* \|	Merge pull request #818 from YosysHQ/clifford/dffsrfix	Clifford Wolf	2019-02-21	1	-6/+7
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\| * \|	Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816	Clifford Wolf	2019-02-21	1	-6/+7
* \| \|	Merge pull request #786 from YosysHQ/pmgen	Clifford Wolf	2019-02-21	14	-59/+1851
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\| * \| \|	Fix typo in passes/pmgen/README.md	Clifford Wolf	2019-02-21	1	-1/+1
\| * \| \|	Bugfix in ice40_dsp	Clifford Wolf	2019-02-21	3	-22/+35
\| * \| \|	Add ice40 test_dsp_map test case generator	Clifford Wolf	2019-02-20	2	-0/+99
\| * \| \|	Add "synth_ice40 -dsp"	Clifford Wolf	2019-02-20	2	-7/+31
\| * \| \|	Add FF support to wreduce	Clifford Wolf	2019-02-20	2	-1/+73
\| * \| \|	Improve iCE40 SB_MAC16 model	Clifford Wolf	2019-02-20	5	-121/+179
\| * \| \|	Detect and reject cases that do not map well to iCE40 DSPs (yet)	Clifford Wolf	2019-02-20	2	-2/+17
\| * \| \|	Add first draft of functional SB_MAC16 model	Clifford Wolf	2019-02-19	4	-53/+467
\| * \| \|	Add actual DSP inference to ice40_dsp pass	Clifford Wolf	2019-02-17	3	-24/+214
\| * \| \|	Merge branch 'master' of github.com:YosysHQ/yosys into pmgen	Clifford Wolf	2019-02-17	28	-199/+627
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\| * \| \| \|	Progress in pmgen	Clifford Wolf	2019-01-15	1	-3/+11
\| * \| \| \|	Progress in pmgen, add pmgen README	Clifford Wolf	2019-01-15	3	-14/+260
\| * \| \| \|	Fix pmgen "reject" statement	Clifford Wolf	2019-01-15	1	-1/+1
\| * \| \| \|	Progress in pmgen	Clifford Wolf	2019-01-15	3	-36/+139
\| * \| \| \|	Progress in pmgen	Clifford Wolf	2019-01-15	3	-21/+157
\| * \| \| \|	Progress in pmgen	Clifford Wolf	2019-01-15	5	-8/+347
\| * \| \| \|	Add mockup .pmg (pattern matcher generator) file	Clifford Wolf	2019-01-15	1	-0/+75
* \| \| \| \|	Merge pull request #821 from eddiehung/dff_init	Clifford Wolf	2019-02-21	1	-4/+2
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\| * \| \| \|	Revert "Add -B option to autotest.sh to append to backend_opts"	Eddie Hung	2019-02-21	1	-4/+2
* \| \| \| \|	Merge pull request #817 from eddiehung/dff_init	Eddie Hung	2019-02-20	1	-21/+0
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\| * \| \| \|	Remove simple_defparam tests	Eddie Hung	2019-02-20	1	-21/+0
* \| \| \| \|	Merge pull request #805 from eddiehung/dff_init	Eddie Hung	2019-02-19	4	-2/+76
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\| * \| \|	Instead of INIT param on cells, use initial statement with hier ref as	Eddie Hung	2019-02-17	1	-18/+13
\| * \| \|	Revert "Add INIT parameter to all ff/latch cells"	Eddie Hung	2019-02-17	2	-86/+43
\| * \| \|	Merge https://github.com/YosysHQ/yosys into dff_init	Eddie Hung	2019-02-17	9	-100/+345
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* \| \| \|	Merge pull request #811 from ucb-bar/firrtlfixes	Clifford Wolf	2019-02-17	6	-56/+298
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\| * \| \| \|	Removed unused variables, functions.	Jim Lawson	2019-02-15	1	-20/+0
\| * \| \| \|	Append (instead of over-writing) EXTRA_FLAGS	Jim Lawson	2019-02-15	1	-1/+1
\| * \| \| \|	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	5	-55/+317
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* \| \| \|	Fix sign handling of real constants	Clifford Wolf	2019-02-13	1	-5/+4
* \| \| \|	Merge pull request #802 from whitequark/write_verilog_async_mem_ports	Clifford Wolf	2019-02-12	1	-38/+41
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\| * \| \| \|	write_verilog: correctly emit asynchronous transparent ports.	whitequark	2019-01-29	1	-38/+41
* \| \| \| \|	Merge pull request #806 from daveshah1/fsm_opt_no_reset	Clifford Wolf	2019-02-12	1	-1/+2
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\| * \| \| \|	fsm_opt: Fix runtime error for FSMs without a reset state	David Shah	2019-02-07	1	-1/+2
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\| \| * \|	Cope WIDTH of ff/latch cells is default of zero	Eddie Hung	2019-02-06	1	-6/+6
\| \| * \|	Remove check for cell->name[0] == '$'	Eddie Hung	2019-02-06	1	-1/+1
\| \| * \|	Refactor	Eddie Hung	2019-02-06	1	-21/+5
\| \| * \|	write_verilog to cope with init attr on q when -noexpr	Eddie Hung	2019-02-06	1	-2/+32
\| \| * \|	Add INIT parameter to all ff/latch cells	Eddie Hung	2019-02-06	2	-43/+86