| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | Remove "write_xaiger -zinit" | Eddie Hung | 2019-10-07 | 1 | -16/+6 | |
| * | | | | | | Add comment on default flop init | Eddie Hung | 2019-10-07 | 1 | -0/+1 | |
| * | | | | | | Get rid of output_port lookup | Eddie Hung | 2019-10-07 | 1 | -14/+8 | |
| * | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 6 | -308/+276 | |
| * | | | | | | Error if $currQ not found | Eddie Hung | 2019-10-05 | 1 | -0/+4 | |
| * | | | | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
| * | | | | | | Fix from merge | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 8 | -184/+33 | |
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| | * | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 2 | -5/+19 | |
| | * | | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
| | * | | | | | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 | |
| | * | | | | | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again | Eddie Hung | 2019-10-04 | 1 | -0/+6 | |
| | * | | | | | Add Const::{begin,end,empty}() | Eddie Hung | 2019-10-04 | 1 | -0/+3 | |
| * | | | | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 | |
| * | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 6 | -21/+14 | |
| * | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 34 | -361/+376 | |
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| | * | | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 34 | -305/+313 | |
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| | * | | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
| | * | | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | * | | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 20 | -86/+374 | |
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| | * | | | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 | |
| | * | | | Update ABC to git rev 623b5e8 | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| | * | | | Bump version | Clifford Wolf | 2019-10-03 | 1 | -1/+1 | |
| | * | | | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 | |
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| | | * | | | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 | |
| | | * | | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 | |
| | * | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 2 | -6/+50 | |
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| | | * | | | | Add quick test | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
| | | * | | | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 | |
| | * | | | | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 2 | -27/+56 | |
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| | | * | | | | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 | |
| | | * | | | | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 2 | -21/+36 | |
| | * | | | | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16 | David Shah | 2019-10-03 | 6 | -2/+184 | |
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| | | * | | | | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 | |
| | | * | | | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 | |
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| | * | | | | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire | Eddie Hung | 2019-10-02 | 2 | -0/+32 | |
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| | | * | | | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 | |
| | | * | | | | | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 | |
| | | * | | | | | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
| | | * | | | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
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| | * | | | / | log_dump() to support State enum | Eddie Hung | 2019-10-02 | 3 | -0/+6 | |
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| | * | | | | Merge pull request #1428 from YosysHQ/clifford/fixbtor | Clifford Wolf | 2019-10-02 | 1 | -6/+9 | |
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| | | * | | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 | |
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| | * | | | Merge pull request #1426 from YosysHQ/mmicko/fix_environ | Miodrag Milanović | 2019-10-01 | 1 | -0/+2 | |
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| | | * | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 | |
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| | * / | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 | |
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| * | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 | |
| * | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
| * | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
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index : iCE40/yosys | |
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