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* Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
* Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
* Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-312-49/+21
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| * Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| * Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
* | Merge pull request #1228 from YosysHQ/dave/yy_buf_sizeEddie Hung2019-07-291-0/+3
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| * | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
* | | Merge pull request #1234 from mmicko/fix_gzip_no_existDavid Shah2019-07-291-19/+21
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| * | Fix case when file does not existMiodrag Milanovic2019-07-291-19/+21
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* | Merge pull request #1226 from YosysHQ/dave/gzipDavid Shah2019-07-278-13/+70
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| * Update CHANGELOGDavid Shah2019-07-261-1/+1
| * Fix frontend auto-detection for gzipped inputDavid Shah2019-07-261-9/+12
| * Add support for reading gzip'd input filesDavid Shah2019-07-266-3/+57
* | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-2517-29/+360
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| * \ Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-254-5/+11
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| | * | intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-234-5/+12
| * | | Merge pull request #1218 from ZirconiumX/synth_intel_iopadsClifford Wolf2019-07-251-8/+8
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| | * | | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
| * | | | Merge pull request #1219 from jakobwenzel/objIteratorClifford Wolf2019-07-252-3/+20
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| | * | | | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
| | * | | | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-242-2/+19
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| * | | | Merge pull request #1224 from YosysHQ/xilinx_fix_ffEddie Hung2019-07-251-2/+2
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| | * | | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
| * | | | Merge pull request #1222 from koriakin/s6-exampleEddie Hung2019-07-245-0/+47
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| | * | | Add a simple example for Spartan 6Marcin Kościelnicki2019-07-245-0/+47
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| * | | Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dspEddie Hung2019-07-233-9/+241
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| | * | | ice40: Fix test_dsp_model.shDavid Shah2019-07-191-1/+1
| | * | | ice40/cells_sim.v: Fix sign of J and K partial productsDavid Shah2019-07-191-5/+7
| | * | | ice40/cells_sim.v: LSB of A/B only signed in 8x8 modeDavid Shah2019-07-191-2/+2
| | * | | Add tests for all combinations of A and B signedness for comb mulEddie Hung2019-07-192-1/+229
| | * | | Don't copy ref if exists alreadyEddie Hung2019-07-191-1/+3
| * | | | Merge pull request #1214 from jakobwenzel/astmod_cloneEddie Hung2019-07-221-0/+2
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| | * | | initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
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| * / / Add "stat -tech cmos"Clifford Wolf2019-07-201-2/+29
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* / / Bump abc to fix &mfs bugEddie Hung2019-07-251-1/+1
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* | Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| * | synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| * | synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| * | synth_intel: revert change to run_max10Dan Ravensloft2019-07-181-1/+1
| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-182-29/+11
| * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
* | | Merge pull request #1207 from ZirconiumX/intel_new_pass_namesDavid Shah2019-07-181-4/+4
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| * | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
* | | Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| * | | write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
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